|Category||Microcontrollers => FPSLIC|
|Description||Configuration Memory Used to Load The Bitstream For AT94K05AL Fpslic Devices.|
|Datasheet||Download ATFS05 datasheet
Designed to Store Configurator Programs for Field Programmable System Level
Integrated Circuits (FPSLICs) In-System Programmable (ISP) via 2-wire Bus Spare Memory Available for System Parameters Storage Low-power CMOS EEPROM Process Available mm 8-lead LAP Package (Pin Compatible Across Product Family) Emulation of Atmel's AT24CXXX Serial EEPROMs Available 10% LV Low-power Standby Mode High-reliability Endurance: 100,000 Write Cycles Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for Commercial Parts (at 70°C)Description
The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration memory for programming Field Programmable System Level Integrated Circuits by using a simple serial-access procedure to configure one or more FPSLIC devices. See Table 1 for a list of supported FPSLIC devices. The FPSLIC Support Device can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable. Table 1. ATFS FPSLIC Support Devices
FPSLIC Device AT94K10 AT94K40 FPSLIC Support Device ATFS10 ATFS40 Configuration Data 226520 Bits 430488 Bits 815382 Bits Spare Memory 35624 Bits 93800 Bits 233194 Bits
The control signals for the FPSLIC Support Device (CE, RESET/OE and CCLK) interface directly with the FPSLIC control signals. All FPSLIC devices can control the entire configuration process and retrieve data from the FPSLIC Support Device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the FPSLIC Support Device. CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the FPSLIC Support Device has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other FPSLIC Support Devices. Upon power-up, the address counter is automatically reset.
8 LAP Pin 2 3 Name DATA CLK RESET/OE I/O I Description Tri-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low). Ground pin. 0.2 µF decoupling capacitor between VCC and GND is recommended. I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. +3.3V power supply pin
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