|Category||Multimedia => Audio => Synthesizers => Dream Sound Synthesis|
|Title||Dream Sound Synthesis|
|Description||Integrated Sound Studio|
|Datasheet||Download ATSAM9707 datasheet
Single-chip Sound Studio with Typical Applications including:
Wavetable Synthesis, Serial MIDI In & Out, MPU-401 (UART) Game-compatible Synthesis with Adlib Interface Effects: Reverb and Chorus DirectsoundTM, Direct3DsoundTM Accelerator with Static Buffer Support Interactive 3-D Positioning Four-channel Surround Four-band Equalizer Mixer High-quality Wavetable Synthesis 16-bit Samples with to 48 kHz Sampling Rate Internal Computations on 28 Bits, DAC Support to 20 Bits Alternate Loop, 24 dB Digital Filter for Each Voice Professional Effects 13 Delay Lines for Resonance-free Stereo Reverb Four-band Final Equalizer Allows Dramatic Sound presence Improvement Expandable Minimum System: + 512K Bytes of ROM x 8 RAM + DAC Maximum System: + 64M Bytes of DRAM + Codec + DAC High Performance RISC Structure for Sound Synthesis/Processing CISC Structure for Host Communication and Housekeeping Audio Transfer at Maximum 16-bit ISA Bus Speed Audio Transfer in Burst Mode: Removes DMA-controlled Transfer Burden Fully Programmable Firmware Downloaded to Memory at Power-up. Easy Software Upgrade. Chip Programming Open to Third-party Software Companies Powerful Programming and Debugging Tools: Algorithm Compiler, Sound Editor, Assembler and Source Debugger. Direct Development from PC Environment, No Special Emulator Required Top Technology Single Low-frequency Crystal Operation and Built-in PLL Minimize RFI 144-lead TQFP Space-saving Package Pin and Function Compatible with ATSAM9407 with Additional Features for Professional Use: Up to Eight Channels of Audio-in Improved Digital Mix Levels and Digital Overflow Handling Improved Tuning Accuracy Additional DSP Micro-instructions and Datapath for More Efficient Audio Processing Algorithm Coding Pin-to-pin replacement for ATSAM9407 requires 3.3V core supply VC3.Description
The is a highly integrated sound processor studio that combines a specialized high-performance RISC-based digital signal processor (synthesis/DSP) and a general-purpose 16-bit CISC-based control processor on a single chip. An on-chip memory management unit (MMU) allows the synthesis/DSP and the control processor to share external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the ISA PC bus, the on-chip MIDI UART and the codec control interface, with minimum intervention from the control processor.
Pin Name GND VC3 VCC D[15:0] Pin Count Type PWR I/O Function Power ground All GND pins should be returned to digital ground. Core power +3.3V nominal to 4.5V). All VC3 pins should be returned to +3.3V. Power +5.5V All VCC pins should be returned to +5V (or 3.3V in case of single 3.3V supply). 16-bit data bus to host processor. Has enough driving power to drive ISA PC bus directly (24 mA buffer). Information on these pins is: - parallel MIDI (MPU-401 type applications) - Adlib control (game sound-type emulation) - Down-/upload of PCM data or application programs Direct ISA PC bus drive requires 5V VCC. Chip select from host, active low Write from host, active low Read from host, active low Selects one of eight internal registers 1: MPU-401 registers 3: 16-bit data (burst DMA mode) - 4-7: game sound registers Tri-state output pin. Can be connected directly to host IRQ line (24 mA). Bus high enable signal, active low. Normally connected to GND. Open drain output buffer (24 mA); driven low during 16-bit burst mode transfers to synchronize PC to the ATSAM9707 memory. Open drain output buffer (24 mA); driven low during 16-bit burst mode transfers. Indicates to host that a 16-bit I/O is in progress. Master reset input, active low. Schmitt trigger input. Crystal connection. Crystal frequency should be fSx256 (typ 11.2896 MHz). Crystal frequency is internally multiplied by four to provide the IC master clock. X1 can also be used as external clock input (3.3V input). X2 CANNOT BE USED TO DRIVE EXTERNAL CIRCUITRY. OUT Two stereo serial audio data outputs (four audio channels). Each output holds 64 bits 32) of serial data per frame. Audio data has precision to 20 bits. DABD0 can hold additional control data (mute, A/D gain, D/A gain, etc.). Audio data bit clock; provides timing to DABD061. Audio data word select. The timing of WSBD can be selected I2S or Japanese compatible. Stereo serial audio data input Serial MIDI_IN input Serial MIDI_OUT output
Pin Name WA[24:0] WD[15:0] RBS Pin Count 16 1 Type OUT I/O OUT Function External memory address (ROM/SRAM). to 32M words (64M 8-bit samples). PCM ROM/SRAM/DRAM data SRAM byte select: Should be connected to the lower RAM address when 8bit wide SRAM is used. The type of RAM (16 bits/8 bits) can be selected by program. PCM ROM chip select, active low. SRAM chip select, active low. SRAM/DRAM write enable, active low. Timing compatible with SIMM DRAM early write feature. PCM ROM/SRAM output enable, active low. Active high, specifies that built-in CPU bootstrap should be used at power-up (case of DRAM connection only). Multiplex DRAM address: 11-, 12-bit multiplex addressing can be used (from x 16-type configurations). DRAM row address strobe DRAM column address strobe General-purpose configurable I/O pins. to P3 can be configured as three additional stereo serial audio data inputs, providing the DAAD with up to eight channels of audio-in. Indicates type of external memory cycle. = 01: Idle or refresh, 00: Synthesis access, 10: Instruction fetch, 11: Processor read/write High when the synthesis is initialized. Can be used as RESET for an external device (CODEC). PLL low pass filter. Should be connected to an external RC network test pin; should be returned to GND. Test pins; should be returned to GND. Power-down, active low.Pin names with an overbar (RAS for example) indicate that the signal is active low.
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