|
Details, datasheet, quote on part number:ATtiny13
| |
| Part: | ATtiny13 |
| Category: | Microcontrollers => 8 bit |
| Description: | 1-Kbyte In-system Programmable Flash Program Memory, 64-Byte SRAM, 64-Byte EePROM, 32-Byte Register File, 4-channel 10-bit A/D, up ... |
| Company: | ATMEL Corporation |
| Datasheet: | Download ATtiny13 datasheet File size : 576 kB |
| Request For quote: | Find where to buy ATtiny13
|
| |
Datasheet text preview:
Features
· High Performance, Low Power AVR® 8-Bit Microcontroller · Advanced RISC Architecture
120 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Througput at 20 MHz Non-volatile Program and Data Memories 1K Byte of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles 64 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles 64 Bytes Internal SRAM Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features One 8-bit Timer/Counter with Prescaler and Two PWM Channels 4-channel, 10-bit ADC with Internal Voltage Reference Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features debugWIRE On-chip Debug System In-System Programmable via SPI Port External and Internal Interrupt Sources Low Power Idle, ADC Noise Reduction, and Power-down Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit Internal Calibrated Oscillator I/O and Packages 8-pin PDIP/SOIC: Six Programmable I/O Lines Operating Voltage: 1.8 - 5.5V for ATtiny13V 2.7 - 5.5V for ATtiny13 Speed Grade ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption Active Mode: 1 MHz, 1.8V: 240µA Power-down Mode: < 0.1µA at 1.8V
·
·
·
8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATtiny13 Preliminary Summary
· · · · ·
Pin Configurations
Figure 1. Pinout ATtiny13
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0)
Rev. 2535DSAVR04/04
Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.
Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced R I S C architecture. By executing powerful instructions in a single clock cycle, the A T ti n y 1 3 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram
Block Diagram
8-BIT DATABUS
STACK POINTER
WATCHDOG OSCILLATOR
CALIBRATED INTERNAL OSCILLATOR
SRAM VCC
WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0
TIMING AND CONTROL
PROGRAM COUNTER GND PROGRAM FLASH
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
INTERRUPT UNIT PROGRAMMING LOGIC
INSTRUCTION DECODER
X Y Z
CONTROL LINES
ALU
DATA EEPROM
STATUS REGISTER
ADC / ANALOG COMPARATOR
DATA REGISTER PORT B
DATA DIR. REG.PORT B
PORT B DRIVERS
RESET CLKI
PB0-PB5
2
ATtiny13
2535DSAVR04/04
ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
Pin Descriptions
VCC GND Port B (PB5..PB0) Digital supply voltage. Ground. Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 49. RESE T Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 12 on page 30. Shorter pulses are not guaranteed to generate a reset.
3
2535DSAVR04/04
Register Summary
Address
0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Name
SREG Reserved SPL Reserved GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL Reserved TCCR0A DWDR Reserved Reserved Reserved Reserved OCR0B GTCCR Reserved CLKPR Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PCMSK DIDR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved Reserved Reserved
Bit 7
I
Bit 6
T
Bit 5
H
Bit 4
S SP[7:0]
Bit 3
V
Bit 2
N
Bit 1
Z
Bit 0
C
Page
page 6 page 8
FOC0A
INT0 INTF0 PUD FOC0B
PCIE PCIF SE
CTPB SM1
OCIE0B O CF0B RFLB SM0 WDRF WGM02
OCIE0A OCF0A P GWRT BORF CS02
TOIE0 TOV0 PGERS ISC01 EXTRF CS01
SELFPRGEN
page 53 page 53 page 70 page 71 page 97 page 70 page 49 page 33 page 66 page 70 page 22
Timer/Counter Output Compare Register A ISC00 PORF CS00
Timer/Counter (8-bit) Oscillator Calibration Register COM0A1 COM0A0 COM0B1 COM0B0 DWDR[7:0] Timer/Counter Output Compare Register B TSM CLKPCE WDTIF WDTIE WDP3 WDCE EEPM1 EEPM0 PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D ACD ADEN ACBG REFS0 ADSC ACO ADLAR ADATE ACI ADIF ACIE ADIE ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 EIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D EEPROM Address Register EEPROM Data Register EERIE EEMWE EEWE EERE WDE WDP2 WDP1 WDP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 PSR10 WGM01 WGM00
page 69 page 94
page 70 page 73 page 24
page 37
page 14 page 14 page 15
page 51 page 51 page 51 page 54 page 76, page 91
page 74 page 88 page 89 page 90 page 90
ADC Data Register High Byte ADC Data Register Low Byte ACME ADTS2 ADTS1 ADTS0
page 91
4
ATtiny13
2535DSAVR04/04
ATtiny13
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5
2535DSAVR04/04
|
|
