|Category||FPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD) => Other Families|
|Description||High-speed, High-density Uv-erasable Programmable Logic Device|
|Datasheet||Download ATV2500BQ-25KC datasheet
Typical 7 ns Pin-to-pin Delay Fully Connected Logic Array with 416 Product Terms Flexible Output Macrocell 48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently Achieves Over 80% Gate Utilization Enhanced Macrocell Configuration Selections D- or T-type Flip-flops Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback Several Power Saving Options Device ATV2500BL ATV2500BQL ICC, Standby 2 mAHigh-speed High-density UV-erasable Programmable Logic Device ATV2500BQ ATV2500BQL
Backward Compatible with ATV2500H/L Software Proven and Reliable High-speed UV EPROM Process Reprogrammable Tested 100% for Programmability 40-lead Dual-in-line and 44-lead Surface Mount Packages
Pin Name IN CLK/IN I/O 0,2,4.. I/O 1,3,5.. GND VCC Note: Function Logic Inputs Pin Clock and Input Bi-directional Buffers "Even" I/O Buffers "Odd" I/O Buffers Ground +5V Supply For ATV2500BQ and ATV2500BQL (PLCC/LCC package only) pin 4 and pin 26 connections are not required.
1. Not required for PLCC versions or ATV2500BQL, making them compatible with ATV2500H and ATV2500L pinout.Description
The ATV2500Bs are the highest density PLDs available or 44-lead package. With their fully connected logic array and flexible macrocell structure, high-gate utilization is easily obtainable. The ATV2500Bs are organized around a single universal and-or array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATV2500Bs, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. Several low-power device options allow selection of the optimum solution for many power-sensitive applications. Each of the options significantly reduces total system power and enhances system reliability.
The ATV2500B functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATV2500Bs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed a 2/4 pattern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
|Related products with the same datasheet|
|Some Part number from the same manufacture ATMEL Corporation|
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