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Part: E5551
Category:
Description:
Company: ATMEL Corporation
Datasheet: Download E5551 datasheet File size : 536 kB
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e5551
Standard R/W Identification IC with Anticollision
Description
The e5551 is a contactless R/W-IDentification IC (IDIC)* for general-purpose applications in the 125 kHz range. A single coil, connected to the chip, serves as the IC's power supply and bidirectional communication interface. Coil and chip together form a transponder. The on-chip 264-bit EEPROM (8 blocks 33 bits each) can be read and written blockwise from a base station. The blocks can be protected against overwriting. One block is reserved for setting the operation modes of the IC. Another block can contain a password to prevent unauthorized writing. Reading occurs by damping the coil by an internal load. There are different bitrates and encoding schemes possible. Writing occurs by interrupting the RF field in a special way.
Features
D Low-power, low-voltage operation D Contactless power supply D Contactless read/write data transmission D Radio Frequency (RF): 100 kHz to 150 kHz D 264 bit EEPROM memory in 8 blocks of 33 bits D 224 bits in 7 blocks of 32 bits are free for user data D Block write protection D Extensive protection against contactless malprogramming of the EEPROM D Anticollision using Answer-On-Request (AOR) D Typical < 50 ms to write and verify a block D Other options set by EEPROM: Bitrate [bit/s]: RF/8, RF/16, RF/32, RF/40 RF/50, RF/64, RF/100, RF/128 Modulation: BIN, FSK, PSK, Manchester, Biphase Other: Terminator mode, Password mode
Transponder Coil interface Power Base station Data
Controller
Memory
e5551
Figure 1. RFID system using e5551 tag
Ordering Information
Extended Type Number e5551A-DOW e5551A-DIT e5551A-FP008 * Package DOW Dice in tray SO8 Remarks
Configuration after production test is an erased memory ('0')
IDIC stands for IDentification Integrated Circuit and is a trademark of Atmel Wireless & Microcontrollers
Rev. A3, 04-Oct-00
1 (21)
e5551
Pads Controller
Pad Window 136 136 mm2 136 136 mm2 78 78 mm2 78 78 mm2 78 78 78 78 mm2 78 mm2 78 mm2 Function 1st coil pad 2nd coil pad Positive supply voltage Negative supply voltage (gnd) Test pad Test pad Test pad The main controller has following functions: D Load mode register with configuration data from EEPROM block 0 after power-on and also during reading D Control memory access (read, write) D Handle write data transmission and the write error modes D The first two bits of the write data stream are the OPcode. There are two valid OP-codes (standard and stop) which are decoded by the controller. D In password mode, the 32 bits received after the OPcode are compared with the stored password in block 7.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ
Test1 Test2 Test3 Coil 2 1 2 8 7 Coil 1
Name Coil1 Coil2 Vdd Vss
Bitrate Generator
The bitrate generator can deliver the following bitrates:
RF/8 - RF/16 - RF/32 - RF/40 - RF/50 - RF/64 - RF/100 - RF/128
e5551
3 4
Note:
6 5
Write Decoder
Decode the detected gaps during writing. Check if write data stream is valid.
Pins 2 to 7 have to be open. They are not specified for applications
Test Logic
Test circuitry allows rapid programming and verification of the IC during test.
Figure 2. Pinning SO8
HV Generator
e5551 Building Blocks
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC's power supply and handles the bidirectional data communication with the reader unit. It consists of the following blocks: D Rectifier to generate a dc supply voltage from the ac coil voltage D Clock extractor D Switchable load between Coil1/ Coil2 for data transmission from the IC to the reader unit (read) D Field gap detector for data transmission from the reader unit into the IC (write)
Voltage pump which generates [18 V for programming of the EEPROM.
Pad Layout
Coil 1
e5551
Coil 2 V DD V SS Test pads
Figure 3. Pad layout
2 (21)
Rev. A3, 04-Oct-00
e5551
Modulator Coil 1 Mode register Analog front end Write decoder Memory (264 bit EEPROM) Controller Bitrate generator Input register POR
Coil 2
Test logic
HV generator
VDD
VSS
Test pads
Figure 4. Block diagram e5551
Power-On Reset (POR)
The power-on reset is a delay reset which is triggered when supply voltage is applied.
D Manchester: rising edge = H; falling edge = L D Biphase: every bit creates a change, a data `H' creates an additional mid-bit change Note: The following modulation type combinations will not work: D Stage1 Manchester or Biphase, stage2 PSK2, at any PSK carrier frequency (because the first stage output frequency is higher than the second stage strobe frequency) D Stage1 Manchester or Biphase and stage2 PSK with bitrate = rf/8 and PSK carrier frequency = rf/8 (for the same reason as above) D Any stage1 option with any PSK for bitrates rf/50 or rf/100 if the PSK carrier frequency is not an integer multiple of the bitrate (e.g., br = rf/50, PSKcf = rf/4, because 50/4 = 12.5). This is because the PSK carrier frequency must maintain constant phase with respect to the bit clock.
Mode Register
The mode register stores the mode data from EEPROM block 0. It is continually refreshed at the start of every block. This increases the reliability of the device (if the originally loaded mode information is false, it will be corrected by subsequent refresh cycles).
Modulator
The modulator consists of several data encoders in two stages, which may be freely combined to obtain the desired modulation. The basic types of modulation are: D PSK: phase shift: 1) every change; 2) every `1'; 3) every rising edge (carrier: fc/2, fc/4 or fc/8) D FSK: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10
Rev. A3, 04-Oct-00
3 (21)
e5551
Memory
The memory of the e5551 is a 264 bit EEPROM, which is arranged in 8 blocks of 33 bits each. All 33 bits of a block, including the lock bit, are programmed simultaneously. The programming voltage is generated on-chip. Block 0 contains the mode data, which are not normally transmitted (see figure 6). Block 1 to 6 are freely programmable. Block 7 may be used as a password. If password protection is not required, it may be used for user data. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lockbit itself) cannot be field-reprogrammed. Data from the memory is transmitted serially, starting with block 1, bit 1, up to block `MAXBLK', bit 32. `MAXBLK' is a mode parameter set by the user to a value
Carrier frequency PSK1 PSK2 Manchester From memory Direct Biphase Mux PSK3 Direct FSK1, 1a FSK2, 2a Mux To load
between 0 and 7 (if maxblk=0, only block 0 will be transmitted).
01 L L L L L L L L User data or password User data User data User data User data User data User data Configuration data 32 bits Not transmitted Figure 5. Memory map 32 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
Figure 6. Modulator block diagram
4 (21)
Rev. A3, 04-Oct-00
e5551
0 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
reserved lock bit (never transmitted)
BR [2] [1] [0]
* "0"
PSKCF MS1 MS2 [1] [0] [2] [1] [0] [1] [0]
MAXBLK * "0" [2] [1] [0] res'd *useSTOP useBT
AOR
useST usePWD
Key: AOR Anwer-On-Request BT use Block Terminator ST use Sequence Terminator PWD use Password STOP obey stop header (active low!) BR Bit Rate MS1 Modulator Stage 1 MS2 Modulator Stage 2 PSKCF PSK Clock Frequency MAXBLK see Maxblock feature reserved do not use * Bit 15 and 24 must always be at "0", otherwise malfunction will appear. 0 0 1 1 0 1 0 1
send blocks: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 to 2 1 to 3 1 to 4 1 to 5 1 to 6 1 to 7
RF/2 RF/4 RF/8 reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
direct psk1 (phase change when input changes) psk2 (phase change on bitclk if input high) psk3 (phase change on rising edge of input) o/p freq. DATA=1 DATA=0 fsk1 rf/8 rf/5 fsk2 rf/8 rf/10 fsk1a rf/5 rf/8 fsk2a rf/10 rf/8
0 0 1 1
0 1 0 1
direct Manchester Biphase reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
RF/8 RF/16 RF/32 RF/40 RF/50 RF/64 RF/100 RF/128
bitrate_8cpb bitrate_16cpb bitrate_32cpb bitrate_40cpb bitrate_50cpb bitrate_64cpb bitrate_100cpb bitrate_128cpb
Figure 7. Memory map of block 0
Rev. A3, 04-Oct-00
5 (21)
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