|Datasheet||Download MG1RT datasheet
The MG1RT series a 0.6 micron 3 metal layers, array based, CMOS product family offering a new frontier in integration and speed. Several arrays to 500k cells cover all system integration needs. The MG1RT is manufactured using SCMOS 2/2 RT, a 0.6 micron drawn, radiation tolerant, 3 metal layers CMOS process. The advanced feature size of the MG1RT translates into high performance with gate delays 250 ps and toggle frequency of 350 MHz. Both 3V and 5V operation are possible for optimum speed/power trade off. The MG1RT series base cell architecture provides high routability of logic with extremely dense compiled memories : ROM, RAM and DPRAM. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery : three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The basic library is designed for optimum speed and area efficiency with logic synthesis software; for example, the register element is 25% smaller than in most competitors libraries. The new delay model included in the simulation libraries gives unprecedented accuracy of the pre-layout and post- layout simulations. The high level function libraries include many common peripheral controllers and several complex circuits derived from the Atmel Wireless & Microcontrollers image and network ASSPs offering. The MG1RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. The MG1RT family continues the Atmel Wireless & Microcontrollers offering in array based for commercial, automotive, industrial, military and space circuits. Design compatibility with previous CMOS and BiCMOS series is assured.Features
D Full Range of Matrices to 480k Cells 0.6 µm Drawn CMOS, 3 Metal Layers, Sea of Gates D High Integration Level : 1000k Equivalent Gates in Memory Intensive Applications D RAM, DPRAM, FIFO Compilers D Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG) D High Speed Performances 250 ps Typical Gate Delay 350 MHz Toggle Frequency D High System Frequency Skew Control 250 MHz PLL for Clock Generation Clock Tree Synthesis Software Volts Operation; Single or Dual Supply Modes D Low Power Consumption 0.9 µW/Gate/Mhz 2.4 µW/Gate/Mhz V D Integrated Power on Reset D Matrices With More than 500 Pads Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator MQFPs packages, to 352 pins GTL & BTL Backplane Driver & Differential Receiver Configurable Drive 48 mA ESD (4 kV) And Latch-up Protected I/O High Noise & EMC Immunity : I/O with Slew Rate Control Internal Decoupling Signal Filtering between Periphery & Core Application Dependent Supply Routing & Several Independent Supply Sources Wide Range of Packages Delivery in Die Form Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor & Synopsys Reference Platforms EDIF & VHDL Reference Formats QML Q and V
to be used when hermetic packaged The maximum number of usable gates is application dependant I/O pads may be configured as VDD or VSS supplies according to circuit requirements This include I/O pads and dedicated pads for supply, PLL...
The core consists of a continuous array of logic cells without routing channels. Each basic cell can implement a logic function such as a two input NAND gate, a memory element (one bit of RAM or DPRAM to 4 bits of ROM); a basic cell can also be a part of a more complex function such as a latch. The metallisation pattern of the logic functions mainly uses the first metal layer, this maximises routing resources for interconnections at the second and third levels of metal. The core supply is implemented via a fixed vertical grid using the second metal layer and a layout dependent horizontal grid using the first and third metal layers. The active core is surrounded by three busses : one interconnection bus close to the array core, one supply
bus powering the core and one interconnection bus close to the periphery. The power bus consists of a VDDA ring using the second metal layer and a VSSA ring using the third metal layer. Integrated decoupling capacitors are located below these buses.
Each side of the die is filled with versatile I/O buffers. Two corners contains PLLs, one a power on reset and one technological devices. Corner pads can be used for PLL I/O's or buffer supplies. Four power rings run above the buffers. The VSSN and VDDN rings supply the output drivers and the VSSQ and VDDQ rings supply the buffer logic.POWER RING Buffer & converter BUFFER COLUMN inner bus
The array core and buffers can have different supply voltages ; in this case the voltage difference is handled by level shifters located close to each I/O buffer. Buffers on different sides of the array can use different supply voltages.
The gate utilisation is the number of equivalent used gates in a design divided by the total number of cells available in the array. The cell structure is designed to provide a gate utilisation % on average random logic designs and 200 % for dual port RAM. The total number of equivalent gates used in an array is the product of gate utilisation by the total number of available cells. This value is design dependent and is influenced by several factors : complexity, operating speed and design structure. As the cell structure is identical for each matrix of the MG1RT family, a better gate utilisation for the smaller arrays may be achieved. Design structure is the dominant factor on gate utilisation ; indeed, as the array has limited routing resources, a higher connection/cell ration implies a lower gate utilisation. Alternatively, regular structures like memories will allow very high gate utilisation to be achieved. The figure below summarises the relation between gate capacity and design style.
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