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Details, datasheet, quote on part number:OAKDSPCORE
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Datasheet text preview:
Features
ˇ 16-bit Fixed-point Digital Signal Processing (DSP) Core ˇ Low-power Consumption: ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ
1 mW/MIPS on 0.25-micron CMOS, 2.5V 0.6 mW/MIPS on 0.20-micron CMOS, 1.8V High Performance: 80 MIPS at 160 MHz (Typical) on 0.25-micron CMOS, 2.5V 100 MIPS at 200 MHz (Typical) on 0.20-micron CMOS, 1.8V Small Die Size: 2.5 mm2 on 0.25-micron CMOS 1.3 mm2 on 0.20-micron CMOS Slow Mode and Stop Mode allow Further Power Reduction Wide Range of Operating Voltage: 1.8V - 3.6V High Level of Modularity: Expandable Data and Program RAM and/or ROM User-definable Registers 64K x 16-bit Data Address Space, 64K x 16-bit Program Address Space Three Parallel Execution Units Wait States are Supported to Link with Slow External Devices Advanced Windows-based Development Tools: Macro Assembler, Linker, C Compiler, Debugger (emulator, simulator) Optional `On-core Emulator' Allows the On-core Debugger, Embedded in the ASIC, to be Run Optional JTAG Serial Interface for On-chip Debug (JCI Interface)
Embedded Digital Signal Processing Core OakDSPCoreŽ
Description
Atmel's embedded OakDSPCoreŽ is a 16-bit general-purpose low-power, low-voltage and high-speed digital signal processor (DSP). It is designed for mid-to-high-end telec o m m u n i c a t i o n s and consumer electronics applications, where low power and por tability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. OakDSPCore is available as a DSP core in Atmel's standard cell library, to be utilized as an engine for DSP-based ASICs. It is specified with several levels of modularity in RAM, ROM and I/O blocks, allowing efficient DSP-based ASIC development. Oa k D S P C o re is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic, power management, etc. The OakDSPCore consists of three main execution units operating in parallel: the Computation/Bit Manipulation Unit (CBU), the Data Address Arithmetic Unit (DAAU) and the Program Control Unit (PCU). The core also contains ROM and RAM addressing units, and Program Control Logic (PCL). All other peripheral blocks, which are ap pl ica tio n specific, are defined as a part of the user-specific logic, implemented around the DSP core on the same silicon die. OakDSPCore has an enhanced set of DSP and general microprocessor functions to m e e t the application requirements. The OakDSPCore programming model and instruction set are aimed at straightforward generation of efficient and compact code.
Rev. 0876F03/01
1
Figure 1. OakDSPCore Symbol
RXSP OMEMSZ4P RYDP GIXDBP
OakDSPCore
On-core Memory
DOCXAP DOCXA10N DRXRM1P DWXRM1P DOEXRM1P DRXRM2P DWXRM2P DOEXRM2P DYAN DYA10N DRYRM1P DWYRM1P DOEYRM1P DRYRM2P DWYRM2P DOEYRM2P PMEMENP
GEXDBP
Off-core Memory
PESCRN PEDSTN DXAP PEDWP PEDRP
BEXTPP GIP
Program Memory
PEXTIP PPAP PPRP PPWP
BFLOATDP BFLOATPP
DMA
PRWEXTP DOFCTRP
BIUSER0P BIUSER1P
User I/O
CUSERO0P CUSERO1P
LINT0P LINT1P LINT2P LNMIP
PIACKN
Interrupts
BTRAPREQP
OCEM
PSTATUSP PTRAPAP PBKENDP DDTVMP PSFTP PDUMMYP
PHI1 PHI2 LRSTP BWAITP BBOOTP
System
2
OakDSPCore
0876F03/01
OakDSPCore
Signal Description
Table 1. Pin Configuration
Signal Name On-core Memory RXSP OMEMSZ4P RYDP GIXDBP DOCXAP DOCXA10N DRXRM1P DWXRM1P DOEXRM1P DRXRM2P DWXRM2P DOEXRM2P DYAN DYA10N DRYRM1P DWYRM1P DOEYRM1P DRYRM2P DWYRM2P DOEYRM2P PMEMENP Off-core Memory GEXDBP PESRCN PEDSTN DXAP PEDWP PEDRP Program Memory BEXTPP GIP PEXTIP PPAP 1 16 1 16 I I/O O O External program indication Instruction data MOVP instruction indication Program address 16 6 6 16 1 1 I/O O O O O O External data bus Source bus Destination bus Off-core XRAM address Data write Data read 16 1 16 16 11 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 I I I I/O O O O O O O O O O O O O O O O O O XRAM data bus Memory size 4K YRAM data bus Internal data bus On-core XRAM address On-core XRAM address - bit 10 On-core XRAM read (lower 1K) On-core XRAM write (lower 1K) On-core XRAM output enable (lower 1K) On-core XRAM read (upper 1K) On-core XRAM write (upper 1K) On-core XRAM output enable (upper 1K) On-core YRAM address On-core YRAM address - bit 10 On-core YRAM read (lower 1K) On-core YRAM write (lower 1K) On-core YRAM output enable (lower 1K) On-core YRAM read (upper 1K) On-core YRAM write (upper 1K) On-core YRAM output enable (upper 1K) Data memory enable Siz e Type Description
3
0876F03/01
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