|Category||Memory => SRAM => SRAM|
|Company||Austin Semiconductor Intl.|
|Datasheet||Download AS5SS128K36-10 datasheet
High frequency and 100% bus utilization Fast cycle times: & 12ns Single +3.3V +5% power supply (VDD) Advanced control logic for minimum control signal interface Individual BYTE WRITE controls may be tied LOW Single R/W\ (READ/WRITE) control pin CKE\ pin to enable clock and suspend operations Three chip enables for simple depth expansion Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed, fully coherent WRITE Internally self-timed, registered outputs to eliminate the need to control OE\ SNOOZE MODE for reduced-power standby Common data inputs and data outputs Linear or Interleaved Burst Modes Burst feature (optional) Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL SRAM Automatic power-down
The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. ASI's 4Mb ZBL SRAMs integrate x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMS are optimized for 100 percent bus utilization, eliminating any turnaround cycles for READ to WRITE, or WRITE to READ, transitions. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE\), two additional chip enables for easy depth expansion (CE2, CE2\), cycle start input (ADV/LD\), synchronous clock enable (CKE\), byte write enables (BWa\, BWb\, BWc\, and BWd\) and read/write (R/ W\). Asynchronous inputs include the output enable (OE\, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The flow-through data-out (Q) is enabled by OE\. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. All READ, WRITE and DESELECT cycles are initiated by the ADV/LD\ input. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV/LD\). Use of burst mode is optional. It is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address. To allow for continuous, 100 percent use of the data bus, the flow-through ZBL SRAM uses a LATE WRITE cycle. For example, if a WRITE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRITE cycle, BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls DQc pins; and BWd\ controls DQd pins. Cycle types can only be defined when an address is loaded, i.e., when ADV/LD\ is LOW. Parity/ECC bits are available on this device. Austin's 4Mb ZBL SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays.OPTIONS
Timing (Access/Cycle/MHz) 8.5ns/11ns/90 MHz 9ns/12ns/83 MHz Packages 100-pin TQFP Operating Temperature Ranges Military to +125oC) Industrial to +85oC)For more products and information please visit our web site at www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SA CE\ CE2 BWd\ BWc\ BWb\ BWa\ CE2\ VDD VSS CLK R/W\ CKE\ OE\ (G\) ADV/LD\ NF SA
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and SA1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls DQc pins; BWd\ controls DQd pins. Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the device. When CKE is HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. Read/Write: This input determines the cycle type when ADV/LD\ is LOW and is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.DESCRIPTION
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge.
Synchronous Chip Enable: These active LOW inputs are used to enable the device and are sampled only when a new external address is loaded (ADV/LD\ LOW). CE2\ can be used for memory depth expansion. Input Synchronous Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD\ LOW). This input can be used for memory depth expansion. Input Output Enable: This active LOW, asynchronous inputs enables the data I/O output drivers. G\ is the JEDEC-standard term for OE\. Input Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When ADV/LD\ is HIGH, R/W\ is ignored. A LOW on ADV/LD\ clocks a new address at the CLK rising edge. Input Mode: This inputs selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. LBO\ is the JEDEC-standard term for MODE. Input/Output SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold times around the rising edge CLK.Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. No Connect: These pins can be left floating or connected to GND to minimize thermal impedance.
Do Not Use: These signals may with be unconnected or wired to GND to minimize thermal impedance. No Function: These pins are internally connected to the die and will have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. Pins 83 and 84 are reserved for address expansion.
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