|Category||Memory => SRAM => SRAM|
|Description||256k X 18 Synchronous Burst SRAM|
|Company||Austin Semiconductor Intl.|
|Datasheet||Download AS5SS256K18-8 datasheet
Fast access times: 8, 10, and 15ns Fast clock speed: 113, 100, and 66 MHz Fast clock and OE\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRTIE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Interally self-timed WRITE cycle Burst control pin (interleaved or linear burst) Automatic power-down Low capacitive bus loading Operating Temperature Ranges: - Military +125oC - Industrial to +85oCSA CE\ CE2 NC bwB\ BWa\ V DD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA
Timing 7.5ns/8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz Packages 100-pin TQFP Operating Temperature Ranges: - Military +125oC - Industrial to +85oC**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Synchronous Burst SRAM family employs high-speed, low power CMOS designs that are fabricated using an advanced CMOS process. ASI's 4Mb Synchronous Burst SRAMs integrate x 18, SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\,
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to two bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on this x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits are available on this device. ASI's 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumŪ, and PowerPC systems and those systems that benefit from a wide synchronous data bus.Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and Conditions the internal use of ADSP\. CE\ is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during WRITE cycle, ADV\ must be HIGH at the rising edge of the first clock after an ADSP\ cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC\, but dependent upon CE\, CE2, and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered CE2 if LOW CE2\ is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE\ is LOW. ADSC\ is also used to place the chip into powerdown state when CE\ is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a lowpower standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup and hold times around the rising edge of CLK.
No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for range. Ground: GND
Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals.INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X01 X...X00
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X01 X...X10FUNCTION READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes
NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be written.
SA1, SA MODE ADV\ CLK ADDRESS REGISTER 18 2 BINARY COUNTER AND LOGIC Q0 CLR 16 18
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
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