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Part: MT5C1009DCJ-15L/XT

Category:
 Memory
   -> SRAM
     -> Async. SRAM
       -> 1 Mb

Description: 128K X 8 SRAM With Chip And Output Enable

Company: Austin Semiconductor Intl.

Datasheet: Download MT5C1009DCJ-15L/XT datasheet     File size : 127 kB

Request For quote: Find where to buy MT5C1009DCJ-15L/XT



Datasheet text preview:
SRAM
Austin Semiconductor, Inc. 128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY SPECIFICATIONS
·SMD 5962-89598 ·MIL-STD-883
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MT5C1009
PIN ASSIGNMENT (Top View)
32-Pin DIP (C, CW) 32-Pin SOJ (SOJ)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 NC WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS
32-Pin LCC (EC) 32-Pin SOJ (DCJ)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CC NE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4
FEATURES
· · · · · · · Access Times: 15, 20, 25, 35, 45, 55 and 70 ns Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS process Single +5V (+10%) Power Supply Easy memory expansion with CE\ and OE\ options. All inputs and outputs are TTL compatible
32-Pin LCC (ECA)
4 3 2 1 32 31 30
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CC NE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4
OPTIONS
· Timing 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access · Package(s)· Ceramic DIP (400 mil) Ceramic DIP (600 mil) Ceramic LCC Ceramic LCC Ceramic Flatpack Ceramic SOJ Ceramic SOJ · 2V data retention/low power
MARKING
-15 -20 -25 -35 -45 -55* -70*
A7 A6 A5 A4 A3 A2 A1 A0 DQ1
5 6 7 8 9 10 11 12 13
A12 A14 A16 0 NC VCC A15 CE2
NC
32-Pin Flat Pack (F)
29 28 27 26 25 24 23 22 21
WE \ A13 A8 A9 A11 OE \ A10 CE1\ DQ8
14 15 16 17 18 19 20
DQ2 DQ3 VSS DQ4 DQ5 DQ6 DQ7
GENERAL DESCRIPTION
C CW EC ECA F DCJ SOJ L No. 111 No. 112 No. 207 No. 208 No. 303 No. 501 No. 507 The MT5C1009 is a 1,048,576-bit high-speed CMOS static RAM organized as 131,072 words by 8 bits. This device uses 8 common input and output lines and has an output enable pin which operate faster than address access times during READ cycle. F o r design flexibility in high-speed memory applications, this device offers chip enable (CE\) and output enable (OE\) features. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled, allowing system designs to achieve low standby power requirements. The "L" version offers a 2V data retention mode, reducing current consumption to 2mW maximum. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. It is particularly well suited for use in high-density, high-speed system applications.
*Electrical characteristics identical to those provided for the 45ns access devices.
For more products and information please visit our web site at www.austinsemiconductor.com
MT5C1009 Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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SRAM
Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM
VCC GND
MT5C1009
A0 A1 A2 A3 A4 A5 A6 A7 A12
ROW DECODER
DQ8
262,144-BIT MEMORY ARRAY
I/O CONTROL
DQ1
CE\ COLUMN DECODER OE\ WE\
A8 A9 A10 A11 A13 A14 A15 A16
POWER DOWN
NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.
TRUTH TABLE
CE\ H X L L L WE\ X X H H L OE\ X X H L X MODE Not Selected Not Selected Output Disable Read Write I/O PIN High-Z High-Z High-Z DOUT DIN SUPPLY CURRENT ISBT2, ISBC2 ISBT2, ISBC2 I CC I CC I CC
MT5C1009 Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range (Vcc).....-0.5V to +6.0V Storage Temperature.....-65°C to +150°C Short Circuit Output Current (per I/O)..20mA Voltage on any Pin Relative to Vss.........-0.5V to +7.0V Max Junction Temperature**......+150°C Power Dissipation ......1 W
MT5C1009
*Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended p e r i o d s will affect reliability. Refer to page 17 of this datasheet for a technical note on this subject. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC & -45oC to +85oC; VCC = 5.0V +10%)
DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0VPARAMETER Power Supply Current: Operating
CONDITIONS CE\ < VIL; OE\ = WE\ = VIH, VCC = MAX, f = MAX = 1/tRC (MIN) Output Open
(1)
SYM ICCSP ICCLP
-15 250 250
-20 140 140
MAX -25 -35 140 130 135 125
-45 125 115
UNITS NOTES mA mA 3
L version only
Power Supply Current: Standby
CE\ > VIH; All Other Inputs VIH, VCC = MAX f = 0 Hz CE\ > VCC -0.2V; VCC = MAX Inputs = VIH or VIL f = 0 Hz
ISBT
25
25
25
25
25
mA
ISBCSP ISBCLP
10 10
10 10
10 10
10 10
10 10
mA mA
CAPACITANCE
DESCRIPTION Input Capacitance (A0-A16) Output Capacitance Input Capacitance (CE\, WE\, OE\)
MT5C1009 Rev. 5.5 8/01
CONDITIONS TA = 25 C, f = 1MHz VCC = 5V
o
SYM CI CO CI
MAX 12 20 14
UNITS pF pF pF
NOTES 4 4 4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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