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Part: J201-204
Category:
Discrete
-> Transistors
-> FETs (Field Effect Transistors)
-> PHEMTs
Description:
Company: Calogic, LLC
Datasheet: Download J201-204 datasheet File size : 213 kB
Request For quote: Find where to buy J201-204
Datasheet text preview:
N-Channel JFET General Purpose Amplifier
CORPORATION
J201 J204 / SST201 SST204
FEATURES ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise specified) Gate-Source or Gate-Drain Voltage . . . . . . . . . . . . . . . . -40V Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC Operating Temperature Range . . . . . . . . . . . -55oC to +135oC Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or an y other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
· High Input Impedance · Low IGSS
PIN CONFIGURATION
SOT-23 G
TO-92
D S
ORDERING INFORMATION
G DS
5010
PRODUCT MARKING (SOT-23) SST2 01 A01 SST2 02 A02 SST2 03 A03 SST2 04 A04
Part
Package
Temperature Range
J201-204 Plastic TO-92 -55oC to +135oC SST201-204 Plastic SOT-23 -55oC to +135oC For Sorted Chips in Carriers see 2N4338 series.
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
SYMBOL IGSS VGS(off) BVGSS IDSS IG gfs gos Ciss Crss en PARAMETER Ga te Reverse Current (Note 1) Gate-So urce Cutoff Voltag e Gate-So urce Breakdown Voltag e Sa tu rati on Drain Current (No te 2) Ga te Current (Note 1) Common-Source Forward 500 Transconductance (Note 2) Co mmo n-So urce Output Conductance Co mmo n-So urce Input Ca pa citan ce Co mmo n-So urce Reverse Tran sfe r Capacitance Eq ui valen t Short-Circuit Inp ut Noise Voltage 1 4 1 5 -0 .3 -40 0.2 -10 1,000 3.5 4 1 5 1.0 201 202 203 204 MIN TYP MAX MIN TYP MAX MI N TYP MAX MIN TYP MAX -100 -1.5 -0 .8 -40 0.9 -10 1,500 10 4 1 5 4.5 -100 -4.0 -2.0 -40 4. 0 -10 20 -100 -10.0 -0.3 -25 0.2 1.2 -10 500 1, 500 µs 2.5 4 pF 1 10 nV H z VDS = 20V, VGS = 0 f = 1MHz (No te 3) VDS = 10V, f = 1kHz VGS = 0 (No te 3) f = 1kHz 3.0 mA pA -100 -2.0 V VDS = 0, IG = -1µA VDS = 20V, VGS = 0 VDG = 20V, ID = IDSS(min) UNITS pA TEST CONDITIONS VDS = 0, VGS = -20V VDS = 20V, ID = 10nA
NOTES: 1. App roxima tely doubles for every 10oC increase in TA. 2. Pulse test duration = 2ms. 3. Fo r design reference only, not 100% tested.
Others parts begin by j2
J2-1
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