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Details, datasheet, quote on part number:34RC02LI-TE13
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| Part: | 34RC02LI-TE13 |
| Category: | Memory => ROM => EEPROM => 2 Kb |
| Description: | 2-kb I2C Serial EePROM, Serial Presence Detect<<<>>>the CAT34RC02 is a 2-kb Serial CMOS EePROM<<<>>>internally Organized as 256 Words of 8 Bits Each. Catalyst S<<<>>>advanced CMOS Technology Substantially Reduces<<<>>>device Power Requirements. The CAT34RC02 Features |
| Company: | Catalyst Semiconductor |
| Datasheet: | Download 34RC02LI-TE13 datasheet File size : 92 kB |
| Request For quote: | Find where to buy 34RC02LI-TE13
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Datasheet text preview:
Preliminary Information
CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect FEATURES
s 400 kHz I2C bus compatible* s 1.7 to 5.5 volt operation s 16-byte page write buffer s Hardware write protection for entire memory s Permanent and reversible software write
H
GEN FR ALO
EE
LE
A D F R E ETM
s Schmitt trigger on SCL and SDA inputs s Low power CMOS technology s 1,000,000 program/erase cycles s 100 year data retention s 8-pin DIP, SOIC, TSSOP and TDFN packages s Industrial and extended temperature ranges
protection for lower 128 bytes
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT34RC02 features a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, SOIC, TSSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 VSS
FUNCTIONAL SYMBOL
SOIC Package (J, W)
1 2 3 4 8 7 6 5 VCC WP SCL SDA
VCC
SCL
TDFN Package (SP2, VP2)
A0 1 A1 2 A2 3 VSS 4 8 VCC 7 WP 6 SCL 5 SDA
A2, A1, A0 WP
CAT34RC02
SDA
VSS
TSSOP Package (U, Y)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Inputs Serial Data/Address Serial Clock Write Protect 1.7 V to 5.5 V Power Supply Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc No. 1052, Rev. F
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CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ......... -55°C to +125°C Storage Temperature ...... -65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ... -2.0 V to VCC + 2.0 V Voltage on A0 ........ -2.0 V to +12.0 V VCC with Respect to VSS ...... -2.0 V to +7.0 V RELIABILITY CHARACTERISTICS Symbol NEND
(2)(*)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 1,000,000 100 4000 100
Units Program/ Erase Cycles Years Volts mA
TDR(2)(*) ILTH(2)(3)
VZAP(2)(*) ESD Susceptibility Latch-up
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Symbol ICC ICC I S B( 4 ) I LI ILO VIL V IH V OL1 V OL2 VHV
Parameter Power Supply Current (Read) Power Supply Current (Write) Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0 V) Output Low Voltage (VCC = 1.7 V) RSWP Set/Clear Overdrive Voltage, (VHV - VCC)
Test Conditions fSCL = 100 kHz fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
Min
Typ 1 3 0 1 1
Max
Units mA mA µA µA µA
1 VCC x 0.7 IOL = 3 mA IOL = 1.5 mA VCC > 2.7 V 5.2 0.4 0.5
VCC x 0.3 VCC + 1.0
V V V V V
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V Symbol CI/O(2) CIN
(2)
Test Input/Output Capacitance (SDA) Input Capacitance (other pins) WP Input Impedance WP Input Impedance
Conditions VI/O = 0 V VIN = 0 V VIN VCC x 0.7
Min
Typ
Max 8 6
Units pF pF k k
Z WPL Z WPH
5 500
70
Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC voltage on address pin A0 is +12.0 V. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to VCC + 1.0 V. (4) Standby Current, ISB = 0 µA (<900 nA).
Doc. No. 1052, Rev. F
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CAT34RC02
A.C. CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits Symbol Parameter 1.7 V - 5.5 V Min F SCL T I (1) t AA t BUF(1) t HD:STA t LOW t HIGH t SU:STA t HD:DAT t SU:DAT t R(1) tF
(1)
2.5 V - 5.5 V Min Max 400 100 0.9 1.3 0.6 1.3 0.6 0.6 0 100 Units kHz ns µs µs µs µs µs µs ns ns 0.3 300 0.6 100 µs ns µs ns
Max 100 100 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 250
1 300
t SU:STO t DH
Power-Up Timing(1)(2) Symbol t PUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
Write Cycle Limits Symbol tW R Parameter Write Cycle Time Min Typ Max 5 Units ms
The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device does not acknowledge external commands.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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Doc No. 1052, Rev. F
CAT34RC02
FUNCTIONAL DESCRIPTION
The CAT34RC02 supports the I2C (2-wire) Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34RC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master alone assigns those roles. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock The serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer data into and out of the device. This pin is an open drain output in transmit mode. A0, A1, A2: Device Address Inputs These inputs set the device address. When left floating, the address pins are internally pulled to ground. WP: Write Protect This input, when grounded or left floating, allows write operations to the entire memory. When this pin is tied to VCC, the entire memory is write protected.
Figure 1. Bus Timing
tF tLOW
tHIGH tLOW
tR
SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL START BIT
Doc. No. 1052, Rev. F
STOP BIT
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CAT34RC02
I2C BUS PROTOCOL
The I2C bus consists of two `wires', SCL and SDA. The two `wires' are connected to the supply (VCC) via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. (1) Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). (2) During a data transfer, the data line must remain stable whenever the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START condition acts as a `wake-up' call for the Slave devices. A Slave will not respond to commands unless the MASTER generates a START condition. STOP Condition The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP condition starts the internal write cycle, when following a WRITE command and sends the Slave into standby mode, when following a READ command.
Device Addressing The Master initiates a data transfer by creating a START condition on the bus. The Master then broadcasts an 8bit serial Slave address. The four most significant bits of the Slave address (the `preamble') are fixed to 1010 (Ah), for normal read/write operations and 0110 (6h) for Software Write Protect (SWP) operations (Fig. 5). The next three bits, A2, A1 and A0, select one of eight possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle. The Slave will aslo acknowledge the 8-bit byte address and every data byte presented in WRITE mode. In READ mode the Slave shifts out eight bits of data, and then `releases' the SDA line durng the 9th clock cycle. If the Master acknowledges in the 9th clock cycle (by pulling down the SDA line), then the Slave continues transmitting. When data transfer is complete, the Master responds with a NoACK (it does not acknowledge the last data byte) and the Slave stops transmitting and waits for a STOP condition.
Figure 4. Acknowledge Timing
SCL FROM MASTER 1 8 9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS 0 1 1 0 A2 A1 A0 R/W Programming the Write Protect Register
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Doc No. 1052, Rev. F
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