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Part: CAT1022RD4E
Category:
Power Management
-> Supervisory Circuits
Description: Supervisory Circuit With I2C Serial 2K CMOS EePROM, Manual Reset And Watchdog Timer Monitors Sda, WP Pin, Active High & Low Reset
Company: Catalyst Semiconductor
Datasheet: Download CAT1022RD4E datasheet File size : 188 kB
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Datasheet text preview:
CAT1021, CAT1022, CAT1023
Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer FEATURES
s Precision power supply voltage monitor s Built-in inadvertent write protection
H
GEN FR ALO
EE
LE
A D F R E ETM
-- 5V, 3.3V and 3V systems -- Five threshold voltage options
s Watchdog timer s Active high or low reset
-- WP pin (CAT1021)
s 1,000,000 Program/Erase cycles s Manual reset input s 100 year data retention s 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
-- Valid reset guaranteed at VCC = 1 V
s 400kHz I C bus s 2.7V to 5.5V operation s Low power CMOS technology s 16-Byte page write buffer
2
(3 x 4.9 mm & 3 x 3 mm foot-print) packages -- TDFN max height is 0.8mm
s Industrial and extended temperature ranges
DESCRIPTION
The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the The CAT1021 and CAT1023 provide a precision VCC supply voltage exceeds the reset threshold level. With both sense circuit and two open drain outputs: one (RESET) active high and low reset signals, interface to microcontrollers drives high and the other (RESET) drives low whenever and other ICs is simple. In addition, the RESET pin or a VCC falls below the reset threshold voltage. The CAT1022 separate input, MR, can be used as an input for push-button has only a RESET output and does not have a Write manual reset capability. Protect input. The CAT1021 also has a Write Protect input (WP). Write operations are disabled if WP is The on-chip, 2k-bit EEPROM memory features a 16-byte page. In addition, hardware data protection is provided by a connected to a logic high. VCC sense circuit that prevents writes to memory whenever All supervisors have a 1.6 second watchdog timer circuit VCC falls below the reset threshold or until VCC reaches the that resets a system to a known state if software or a reset threshold during power up. hardware glitch halts or "hangs" the system. For the CAT1021 and CAT1022, the watchdog timer monitors Available packages include an 8-pin DIP and surface mount the SDA signal. The CAT1023 has a separate watchdog 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP timer interrupt input pin, WDI. packages. The TDFN package thickness is 0.8mm maximum. TDFN footprint options are 3x3mm or 3x4.9mm (MSOP pad layout). The CAT1021, CAT1022 and CAT1023 are complete memory and supervisory solutions for microcontrollerbased systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS technology. Memory interface is via a 400kHz I2C bus.
© 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
Doc No. 3009, Rev. H
CAT1021, CAT1022, CAT1023
BLOCK DIAGRAM
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
Threshold Voltage Options
Part Dash Minimum Number Threshold
-45 -42 -30 -28 -25 4.50 4.25 3.00 2.85 2.55
Maximum T h r e s h o ld
4.75 4.50 3.15 3.00 2.70
SDA
START/STOP LOGIC 2kbit EE PROM
XDEC WP (CAT1021) CONTROL LOGIC
DATA IN STORAGE
HIGH VOLTAGE/ TIMING CONTROL RESET Controller Precision MR
Vcc Monitor
STATE COUNTERS SLAVE ADDRESS COMPARATORS
SCL
RESET (CAT1021/23)
RESET
WDI (CAT1023)
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (S, V) TSSOP Package (U, Y) MSOP Package (R, Z)
MR 1 RESET 2 WP 3 VSS 4 8 VCC CAT1021 7 RESET 6 SCL 5 SDA
(Bottom View) TDFN Package: 3mm x 4.9mm 0.8mm maximum height - (RD2, ZD2)
VCC RESET SCL SDA
8 7 1 2
(Bottom View) TDFN Package: 3mm x 3mm 0.8mm maximum height - (RD4, ZD4)
VCC RESET SCL SDA
8 7 1 2
MR RESET WP VSS
MR RESET WP VSS
CAT1021
6 5
CAT1021
6 5
3 4
3 4
MR 1 RESET 2 NC 3 VSS 4 CAT1022
8 VCC 7 NC 6 SCL 5 SDA
VCC NC SCL SDA
8 7
1 2
MR RESET NC VSS
VCC NC SCL SDA
8 7
1 2
MR RESET NC VSS
CAT1022
6 5
3 4
CAT1022
6 5
3 4
MR 1 RESET 2 RESET 3 VSS 4 CAT1023
8 VCC 7 WDI 6 SCL 5 SDA
VCC WDI SCL SDA
8 7
1 2
MR RESET RESET VSS
VCC 8 WDI 7 SCL 6 SDA 5
1 MR 2 RESET
CAT1023
6 5
3 4
CAT1023
3 RESET 4V SS
Doc. No. 3009, Rev. H
2
CAT1021, CAT1022, CAT1023
PIN DESCRIPTION
RESET/RESET: RESET OUTPUTS (RESET CAT1021/23 Only) These are open drain pins and RESET can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET pin must be connected through a pull-up resistor. SDA: SERIAL DATA ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input.
MANUAL RESET INPUT MR: Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset condition. Reset outputs are active while MR input is low and for the reset timeout period after MR returns to high. The input has an internal pull up resistor. WP (CAT1021 Only): WRITE PROTECT INPUT When WP input is tied to VSS or left unconnected write operations to the entire array are allowed. When tied to VCC, the entire array is protected. This input has an internal pull down resistor. WDI (CAT1023 Only): WATCHDOG TIMER INTERRUPT Watchdog Timer Interrupt Input is used to reset the watchdog timer. If a transition from high to low or low to high does not occur every 1.6 seconds, the RESET outputs will be driven active.
PIN FUNCTIONS
Pin Name
NC RESET VSS SDA SCL RESET VCC WP MR WDI
OPERATING TEMPERATURE RANGE
Industrial Extended -40°C to 85°C -40°C to 125°C
Function
No Connect Active Low Reset Input/Output Ground Serial Data/Address Clock Input Active High Reset Output (CAT1021/23) Power Supply Write Protect (CAT1021 only) Manual Reset Input Watchdog Timer Interrupt (CAT1023)
CAT102X FAMILY OVERVIEW
Device Manual Reset Input Pin Watchdog Watchdog Monitor Pin SDA SDA WDI Write Protection Pin Independent Auxiliary Voltage Sense RESET: Active High and LOW EEPROM
CAT1021 CAT1022 CAT1023 CAT1024 CAT1025 CAT1026 CAT1027
2k 2k 2k 2k 2k 2k
WDI
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
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Doc No. 3009, Rev. H
CAT1021, CAT1022, CAT1023
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ........ 55°C to +125°C Storage Temperature ..... 65°C to +150°C Voltage on any Pin with Respect to Ground(1) .. 2.0 V to VCC + 2.0 V VCC with Respect to Ground ....... 2.0V to 7.0 V Package Power Dissipation Capability (TA = 25°C) .......... 1.0 W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(2) ...... 100 mA
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time.
DC OPERATING CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol ILI ILO ICC1 ICC2 ISB VIL(1) VIH(1) VOL VOH
Parameter Input Leakage Current Output Leakage Current Power Supply Current (Write) Power Supply Current (Read) Standby Current Input Low Voltage Input High Voltage Output Low Voltage (SDA, RESET) Output High Voltage (RESET)
Test Conditions VIN = GND to Vcc VIN = GND to Vcc fSCL = 400 kHz VCC = 5.5V fSCL = 400 kHz VCC = 5.5 V Vcc = 5.5 V, VIN = GND or Vcc
Min -2 -10
Typ
Max 10 10 3 1 60
Units µA µA mA mA µA V V V V
-0.5 0.7 x Vcc IOL = 3 mA VCC = 2.7 V IOH = -0.4 mA VCC = 2.7 V CAT102x-45 (VCC = 5.0 V) CAT102x-42 (VCC = 5.0 V) Vcc 0.75 4.50 4.25 3.00 2.85 2.55 1.00 15
0.3 x Vcc Vcc + 0.5 0.4
4.75 4.50 3.15 3.00 2.70 V mV V
VTH
Reset Threshold
CAT102x-30 (VCC = 3.3 V) CAT102x-28 (VCC = 3.3 V) CAT102x-25 (VCC = 3.0 V)
VRVALID VRT(2)
Reset Output Valid VCC Voltage Reset Threshold Hysteresis
Notes: 1. VIL min and VIH max are reference values only and are not tested. 2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3009, Rev. H
4
CAT1021, CAT1022, CAT1023
CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol COUT
(1)
Test Output Capacitance Input Capacitance
Test Conditions VOUT = 0V VIN = 0V
Max 8 6
Units pF pF
CIN(1)
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol fSCL tSP tLOW tHIGH tR(1) tF(1) tHD;STA tSU;STA tHD;DAT tSU;DAT tSU;STO tAA tDH tBUF(1) tWC(3) Parameter Clock Frequency Input Filter Spike Suppression (SDA, SCL) Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time (for a Repeated Start) Data Input Hold Time Data Input Setup Time Stop Condition Setup Time SCL Low to Data Out Valid Data Out Hold Time Time the Bus must be Free Before a New Transmission Can Start Write Cycle Time (Byte or Page) 50 1.3 5 0.6 0.6 0 100 0.6 900 1.3 0.6 300 300 Min Max 400 100 Units kHz ns µs µs ns ns µs µs ns ns µs ns ns µs ms
Notes: 1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 2. Test Conditions according to "AC Test Conditions" table. 3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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Doc No. 3009, Rev. H
Others parts begin by ca
CA-1 CA-2 CA-3 CA-4 CA-5 CA-6 CA-7 CA-8 CA-9 CA-10 CA-11 CA-12 CA-13 CA-14 CA-15 CA-16 CA-17 CA-18 CA-19 CA-20 CA-21 CA-22 CA-23 CA-24 CA-25 CA-26 CA-27 CA-28 CA-29 CA-30 CA-31 CA-32 CA-33 CA-34 CA-35 CA-36 CA-37 CA-38 CA-39 CA-40 CA-41 CA-42
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