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Part: CAT24C082
Category:
Power Management
-> Supervisory Circuits
-> System Supervisors/Reset
Description: Supervisory Circuits With I2c Serial CMOS E2PROM, Precision Reset Controller And Watchdog Timer
Company: Catalyst Semiconductor
Datasheet: Download CAT24C082 datasheet File size : 363 kB
Request For quote: Find where to buy CAT24C082
Datasheet text preview:
Advanced
CAT24C161/162(16K), CAT24C081/082(8K) CAT24C041/042(4K), CAT24C021/022(2K)
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s Watchdog Timer on SDA for 24CXX1 s Programmable Reset Threshold s 400 KHz I2C Bus Compatible s 2.7 to 6 Volt Operation s Low Power CMOS Technology s 16 - Byte Page Write Buffer s Built-in inadvertent write protection s s s s s Active High or Low Reset Outputs
-- VCC Lock Out
-- Precision Power Supply Voltage Monitoring -- 5V, 3.3V and 3V options 1,000,000 Program/Erase Cycles 100 Year Data Retention 8-Pin DIP or 8-Pin SOIC Commercial, Industrial and Automotive Temperature Ranges
DESCRIPTION
The CAT24CXXX is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The 24C161/162(16K), 24C081/082(8K), 24C041/042(4K) and 24C021/022(2K) feature a I2C Serial CMOS EEPROM. Catalyst's advanced CMOS technology substantially reduces device power requirements. The 24CXXX features a 16-byte page and is available in 8-pin DIP or 8-pin SOIC packages. The reset function of the 24CXXX protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. 24CXXX features active low reset on pin 2 and active high reset on pin 7. 24CXX1 features watchdog timer on the SDA line. 24CXX2 does not feature the watchdog timer function.
PIN CONFIGURATION
24CXX1/XX2*
DC RESET WP VSS VCC RESET SCL SDA
BLOCK DIAGRAM
EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS
*All products offered in P and J packages
SDA
START/STOP LOGIC
PIN FUNCTIONS
XDEC
E2PROM
Pin Name SDA RESET/RESET SCL Vcc DC VSS WP
Function Serial Data/Address Reset I/O Clock Input Power Supply Do Not Connect Ground Write Protect
WP
CONTROL LOGIC
DATA IN STORAGE
HIGH VOLTAGE/ TIMING CONTROL RESET Controller
Only for 24C161 WATCHDOG
STATE COUNTERS SLAVE ADDRESS COMPARATORS
SCL
High Precision
Vcc Monitor
RESET/RESET
24C1601 BLOCK
© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
Advanced
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias...........55°C to +125°C Storage Temperature...... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .....2.0V to +VCC + 2.0V
COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
VCC with Respect to Ground.........2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C)1.0W.........1.0W Lead Soldering Temperature (10 secs)......300°C Output Short Circuit Current(2) ..100mA
RELIABILITY CHARACTERISTICS
Symbol N END (3) T DR
(3) (3)
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min. 1,000,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
VZ A P
I LTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Symbol I CC Isb
Parameter Power Supply Current Standby Current
Min.
Limits Typ. Max. 3 40 50
Units mA µA µA µA µA V V V
Test Conditions f SCL = 100 KHz Vcc=3.3V Vcc=5 VIN=GND or VCC VIN=GND or VCC
ILI ILO VIL VIH VOL
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (SDA) 1 VCC x 0.7
2 10 VCC x 0.3 VCC + 0.5 0.4
IOL = 3 mA ,VCC=3.0V
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(3) CI N
(3)
Test Input/Output Capacitance (SDA) Input Capacitance (SCL)
Max. 8 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
Doc. No. 25079-00 1/98 M-1
2
Advanced
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF
CAT24CXX1/XX2
Read & Write Cycle Limits Symbol Parameter VCC=2.7V - 6V Min. FS C L TI ( 1 ) t AA tBUF(1) t HD:STA t LOW t HIGH t SU:STA t HD:DAT t SU:DAT tR
(1)
VCC=4.5V - 5.5V Min. Max. 400 200 1 1.2 0.6 1.2 0.6 0.6 0 50 Units kHz ns µs µs µs µs µs µs ns ns 0.3 300 0.6 100 µs ns µs ns
Max. 100 200 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50
1 300
tF(1) t SU:STO t DH
Power-Up Timing(1)(2) Symbol t PUR t PUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits Symbol t WR Parameter Write Cycle Time Min. Typ. Max 10 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
3
Doc. No. 25079-00 1/98 M-1
CAT24CXX1/XX2
Advanced
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH VRT VOLRS VOHRS
Parameter
Glitch Reject Pulse Width Reset Threshold Hystersis Reset Output Low Voltage (IOLRS=1mA) Reset Output High Voltage Reset Threshold (Vcc=5V) (24CXXX-45) Reset Threshold (Vcc=5V) (24CXXX-42)
Min.
Max.
100
Units
ns mV
15 0.4 Vcc-0.75 4.50 4.25 3.00 2.85 2.55 130 4.75 4.50
V V
V 3.15 3.00 2.70 270 5 1 ms µs V
VTH
Reset Threshold (Vcc=3.3V) (24CXXX-30) Reset Threshold (Vcc=3.3V) (24CXXX-28) Reset Threshold (Vcc=3V) (24CXXX-25)
tPURST tRPD
Power-Up Reset Timeout VTH to RESET Output Delay RESET Output Valid
VRVALID
Doc. No. 25079-00 1/98 M-1
4
Advanced
CAT24CXX1/XX2
PIN DESCRIPTIONS
WP: WRITE PROTECT If the pin is tied to VCC the entire memory array becomes Write Protected (READ only). When the pin is tied to VSS or left floating normal read/write operations are allowed to the device. SCL: SERIAL CLOCK The serial clock input clocks all data transferred into or out of the device. RESET/RESET: RESET I/O These are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition for approximately 200ms. RESET pin must be connected through a pull-down and RESET pin must be connected through a pull-up device. SDA: SERIAL DATA/ADDRESS The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. In the 24CXX1, the SDA line is also used as the Watchdog Timer Monitor. VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID). The RESET pins are I/Os; therefore, the CAT24CXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 24CXXX will initiate a reset timeout after detecting a high and the RESET input in the 24CXXX will initiate a reset timeout after detecting a low.
Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT24CXX1 will respond with a reset signal after a timeout interval of 1.6 seconds for lack of activity. 24CXX1 is designed with the Watchdog Timer feature on the SDA input. For the 24CXX1, if the microcontroller does not toggle the SDA input pin within 1.6 seconds the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watchdog Timer is cleared by any transition on SDA. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. 24CXX2 does not feature the Watchdog Timer function.
DEVICE OPERATION
Reset Controller Description
The CAT24CXXX provides a precision RESET controller that ensures correct system operation during brownout and power-up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until VCC reaches the
Figure 1. RESET Output Timing
t
GLITCH
VTH VRVALID VCC t PURST t RPD t PURST
RESET
t RPD
RESET
5
Doc. No. 25079-00 1/98 M-1
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