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Part: CAT28F002T-12BT
Category:
Memory
-> Flash
-> Parallel Flash
-> 2M
Description: 120ns 2M-bit CMOS Boot Block Flash Memory
Company: Catalyst Semiconductor
Datasheet: Download CAT28F002T-12BT datasheet File size : 359 kB
Request For quote: Find where to buy CAT28F002T-12BT
Datasheet text preview:
CAT28F002
2 Megabit CMOS Boot Block Flash Memory FEATURES
s Fast Read Access Time: 90/120/150 ns s On-Chip Address and Data Latches s Blocked Architecture: s Electronic Signature
Licensed Intel second source
s 100,000 Program/Erase Cycles and 10 Year
Data Retention
s Standard Pinouts:
-- One 16-KB Protected Boot Block · Top or Bottom Locations -- Two 8-KB Parameter Blocks -- One 96-KB Main Block -- One 128-KB Main Block
s Hardware Data Protection s Automated Program and Erase Algorithms s Automatic Power Savings Feature s Low Power CMOS Operation s 12.0V
-- 40-Lead TSOP -- 40-Lead PDIP
s High Speed Programming s Commercial, Industrial and Automotive Tem-
perature Ranges
s Reset/Deep PowerDown Mode
-- 0.2µA ICC Typical -- Acts as Reset for Boot Operations
± 5% Programming and Erase Voltage
DESCRIPTION
The CAT28F002 is a high speed 256K X 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates. The CAT28F002 has a blocked architecture with one 16 KB Boot Block, two 8 KB Parameter Blocks, one 96 KB Main Block and one 128 KB Main Block. The Boot Block section can be at the top or bottom of the memory map. The Boot Block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other locations of CAT28F002. The CAT28F002 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F002 is also designed with onChip Address Latches, Data Latches, Programming and Erase Algorithms. A deep power-down mode lowers the total Vcc power consumption 1µw typical. The CAT28F002 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin TSOP and 40-pin PDIP packages.
BLOCK DIAGRAM
ADDRESS COUNTER WRITE STATE MACHINE RP WE COMMAND REGISTER PROGRAM VOLTAGE SWITCH CE, OE LOGIC ERASE VOLTAGE SWITCH
I/O0I/O7
I/O BUFFERS
STATUS REGISTER DATA LATCH
COMPARATOR ADDRESS LATCH
SENSE AMP
CE OE
Y-GATING Y-DECODER 16K-BYTE BOOT BLOCK 8K-BYTE PARAMETER BLOCK 8K-BYTE PARAMETER BLOCK 96K-BYTE MAIN BLOCK 128K-BYTE MAIN BLOCK
A0A17 VOLTAGE VERIFY SWITCH
X-DECODER
28F002 F01
© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 25072-00 2/98 F-1
CAT28F002
PIN CONFIGURATION
PDIP Package (P)
NC NC A0 CE GND OE I/O0 I/O1 I/O2 I/O3 VCC VCC I/O4 I/O5 I/O6 I/O7 A10 GND A17 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC A1 A2 A3 A4 A5 A6 A7 VPP RP WE A8 A9 A11 A12 A13 A14 A15 A16 NC
TSOP Package (T)
A17 GND NC NC A10 I/O7 I/O6 I/O5 I/O4 VCC VCC NC I/O3 I/O2 I/O1 I/O0 OE GND CE A0
A16 A15 A14 A13 A12 A11 A9 A8 WE RP VPP DU NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PIN FUNCTIONS
Pin Name A0A17 I/O0I/O7 CE OE WE VCC VSS VPP RP DU Input Type Input I/O Input Input Input Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply Power Down Do Not Use
28F002 F03
Doc. No. 25072-00 2/98 F-1
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CAT28F002
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .......... 55°C to +95°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .. 2.0V to +VCC + 2.0V Voltage on Pin A9 with Respect to Ground(1) .......... 2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) ..... 2.0V to +14.0V VCC with Respect to Ground(1) ... 2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) .......... 1.0 W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(2) ...... 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS Symbol NEND
(3)
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 100K 10 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
CAPACITANCE TA = 25°C, f = 1.0 MHz Limits Symbol CIN(3) COUT(3) CVPP(3) Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance Min Max. 8 12 25 Units pF pF pF Conditions VIN = 0V VOUT = 0V VPP = 0V
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
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Doc. No. 25072-00 2/98 F-1
CAT28F002
D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified Limits Symbol ILI ILO ISB1 ISB2 IPPD ICC1 ICC2(1) ICC3(1) IPPS IPP1 IPP2(1) IPP3(1) VIL VOL VIH VOH1 VID IID ICCD ICCES IPPES IRP VOH2 Parameter Input Leakage Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VPP Deep Powerdown Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current Input Low Level Output Low Level Input High Level Output High Level TTL A9 Signature Voltage A9 Signature Current VCC Deep Powerdown Current VCC Erase Suspend Current VPP Erase Suspend Current RP Boot Block Unlock Current Output High Level TTL 0.85 VCC 2.0 2.4 10.8 13.2 500 1.0 10 200 500 0.5 Min. Max. ±1.0 ±10 100 1.5 5.0 55 50 30 ±10 200 200 20 15 0.8 0.45 VCC+0.5 Unit µA µA µA mA µA mA mA mA µA µA µA mA mA V V V V V µA µA mA µA µA V IOH = -2.5mA, VCC = 4.5V A9 = VID A9 = VID RP = GND±0.2V Erase Suspended CE = VIH Erase Suspended VPP=VPPH RP = VHH VCC = VCCMIN IOH = -1.5mA IOL = 5.8mA, VCC = 4.5V Test Conditions VIN = VCC or VSS VCC = 5.5V VOUT = VCC or VSS, VCC = 5.5V CE = VCC ±0.2V = RP VCC = 5.5V CE = RP = VIH, VCC = 5.5V RP = GND±0.2V VCC = 5.5V, CE = GND, IOUT = 0mA, f = 10 MHz VCC = 5.5V, Programming in Progress VCC = 5.5V, Erase in Progress VPP VCC VPP = VPPH VPP = VPPH, Programming in Progress VPP = VPPH, Erase in Progress
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
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CAT28F002
SUPPLY CHARACTERISTICS Limits Symbol VLKO VCC VPPL VPPH VHH VPPLK Parameter VCC Erase/Write Lock Voltage VCC Supply Voltage VPP During Read Operations VPP During Erase/Program RP, OE Unlock Voltage VPP Lock-Out Voltage Min 2.0 4.5 0 11.4 10.8 0 5.5 6.5 12.6 13.2 6.5 Max. Unit V V V V V V
A.C. CHARACTERISTICS, Read Operation VCC = +5V ±10%, unless otherwise specified JEDEC Standard Symbol tAVAV tELQV tAVQV tGLQV tGLQX tELQX tGHQZ tEHQZ tPHQV Symbol tRC tCE tACC tOE tOH
(1)(6)
28F002-90 Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time Output Hold from Address OE/CE Change 0 0 0 30 30 300 Min. Max. 90 90 90 40
28F002-12 28F002-15 Min. Max. Min. Max. Unit 120 120 120 40 0 0 0 30 30 300 0 0 0 30 30 300 150 150 150 40 ns ns ns ns ns ns ns ns ns ns
tOLZ(1)(6) OE to Output in Low-Z tLZ CE to Output in Low-Z OE High to Output High-Z CE High to Output High-Z RP High to Output Delay tDF(1)(2) tHZ(1)(2) tPWH
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V INPUT PULSE LEVELS 0.45 V 0.8 V
5108 FHD F03
2.0 V REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF
5108 FHD F04
CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. (5) Input and Output Timing Reference = 0.8V and 2.0V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
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Doc. No. 25072-00 2/98 F-1
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