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Part: CAT28F010-70
Category:
Memory
-> Flash
Description: 1 Megabit CMOS Flash Memory
Company: Catalyst Semiconductor
Datasheet: Download CAT28F010-70 datasheet File size : 359 kB
Request For quote: Find where to buy CAT28F010-70
Datasheet text preview:
CAT28F010
1 Megabit CMOS Flash Memory FEATURES
s Fast Read Access Time: 70/90/120 ns s Low Power CMOS Dissipation:
Licensed Intel second source
s Commercial, Industrial and Automotive
Temperature Ranges
s On-Chip Address and Data Latches s JEDEC Standard Pinouts:
Active: 30 mA max (CMOS/TTL levels) Standby: 1 mA max (TTL levels) Standby: 100 µA max (CMOS levels)
s High Speed Programming:
10 µs per byte 2 Sec Typ Chip Program
32-pin DIP 32-pin PLCC 32-pin TSOP (8 x 20)
s 100,000 Program/Erase Cycles s 10 Year Data Retention s Electronic Signature
s 0.5 Seconds Typical Chip-Erase s 12.0V
± 5% Programming and Erase Voltage
s Stop Timer for Program/Erase
DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation. The CAT28F010 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages.
I/O0I/O7
BLOCK DIAGRAM
I/O BUFFERS ERASE VOLTAGE SWITCH
WE
COMMAND REGISTER
PROGRAM VOLTAGE SWITCH
CE, OE LOGIC
DATA LATCH
SENSE AMP
CE OE
ADDRESS LATCH
Y-GATING Y-DECODER 1,048,576 BIT MEMORY ARRAY
5108 FHD F02
A0A16
X-DECODER
VOLTAGE VERIFY SWITCH
© 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1019, Rev. A
CAT28F010
PIN CONFIGURATION
DIP Package (P)
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE N/C A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PIN FUNCTIONS
Pin Name A0A16
PLCC Package (N)
VPP VCC A12 A15 A16 WE N/C
Type Input I/O Input Input Input
Function Address Inputs for memory addressing Data Input/Output Chip Enable Output Enable Write Enable Voltage Supply Ground Program/Erase Voltage Supply
I/O0I/O7 CE
29 28 27 26 25 24 23 A14 A13 A8 A9 A11 OE A10 CE I/O7
4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11
OE WE VCC VSS VPP
12 22 13 21 14 15 16 17 18 19 20
I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6
5108 FHD F01
5108 FHD F01
TSOP Package (Standard Pinout 8mm x 20mm) (T)
A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
TSOP Package (Reverse Pinout) (TR)
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4
5108 FHD F14
Doc. No. 1019, Rev. A
2
CAT28F010
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .......... 55°C to +95°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .. 2.0V to +VCC + 2.0V Voltage on Pin A9 with Respect to Ground(1) .......... 2.0V to +13.5V VPP with Respect to Ground during Program/Erase(1) ..... 2.0V to +14.0V VCC with Respect to Ground(1) ... 2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) .......... 1.0 W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(2) ...... 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 100K 10 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(3) VZAP(3) ILTH(3)(4)
CAPACITANCE TA = 25°C, f = 1.0 MHz Limits Symbol CIN
(3)
Test Input Pin Capacitance Output Pin Capacitance VPP Supply Capacitance
Min
Max. 6 10 25
Units pF pF pF
Conditions VIN = 0V VOUT = 0V VPP = 0V
COUT(3) CVPP
(3)
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
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Doc. No. 1019, Rev. A
CAT28F010
D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified. Limits Symbol ILI ILO ISB1 ISB2 ICC1 ICC2(1) ICC3(1) ICC4(1) IPPS IPP1 IPP2(1) IPP3(1) IPP4(1) VIL VILC VOL VIH VIHC VOH1 VOH2 VID IID(1) VLO Parameter Input Leakage Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current VCC Programming Current VCC Erase Current VCC Prog./Erase Verify Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current VPP Prog./Erase Verify Current Input Low Level TTL Input Low Level CMOS Output Low Level Input High Level TTL Input High Level CMOS Output High Level TTL Output High Level CMOS A9 Signature Voltage A9 Signature Current VCC Erase/Prog. Lockout Voltage 2.5 2 VCC*0.7 2.4 VCC0.4 11.4 13 200 0.5 0.5 Min. Max. ±1 ±1 100 1 30 15 15 15 ± 10 200 30 30 5 0.8 0.8 0.45 VCC+0.5 VCC+0.5 Unit µA µA µA mA mA mA mA mA µA µA mA mA mA V V V V V V V V µA V IOH = 2.5mA, VCC = 4.5V IOH = 400µA, VCC = 4.5V A9 = VID A9 = VID IOL = 5.8mA, VCC = 4.5V Test Conditions VIN = VCC or VSS VCC = 5.5V, OE = VIH VOUT = VCC or VSS, VCC = 5.5V, OE = VIH CE = VCC ±0.5V, VCC = 5.5V CE = VIH, VCC = 5.5V VCC = 5.5V, CE = VIL, IOUT = 0mA, f = 6 MHz VCC = 5.5V, Programming in Progress VCC = 5.5V, Erasure in Progress VCC = 5.5V, Program or Erase Verify in Progress VPP = VPPL VPP = VPPH VPP = VPPH, Programming in Progress VPP = VPPH, Erasure in Progress VPP = VPPH, Program or Erase Verify in Progress
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1019, Rev. A
4
CAT28F010
SUPPLY CHARACTERISTICS Limits Symbol VCC VPPL VPPH Parameter VCC Supply Voltage VPP During Read Operations VPP During Read/Erase/Program Min 4.5 0 11.4 Max. 5.5 6.5 12.6 Unit V V V
A.C. CHARACTERISTICS, Read Operation VCC = +5V ±10%, unless otherwise specified. 28F010-70(8) JEDEC Standard Symbol Symbol Parameter tAVAV tELQV tAVQV tGLQV tAXQX tGLQX tELZX tGHQZ tEHQZ tWHGL(1) tRC tCE tACC tOE tOH tOLZ(1)(6) tLZ(1)(6) tDF(1)(2) tDF(1)(2) Read Cycle Time CE Access Time Address Access Time OE Access Time Output Hold from Address OE/CE Change OE to Output in Low-Z CE to Output in Low-Z OE High to Output High-Z CE High to Output High-Z Write Recovery Time Before Read 6 0 0 0 20 30 6 Min. Max. 70 70 70 28 0 0 0 20 30 6 28F010-90(7) 28F010-12(7) Min. Max. Min. Max. 90 90 90 35 0 0 0 30 40 120 120 120 50 Unit ns ns ns ns ns ns ns ns ns µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V INPUT PULSE LEVELS 0.45 V 0.8 V 2.0 V REFERENCE POINTS
Figure 2. Highspeed A.C. Testing Input/Output Waveform(3)(4)(5)
3.0 V INPUT PULSE LEVELS 0.0 V 1.5 V REFERENCE POINTS
5108 FHD F03
5108 FHD F03A
Testing Load Circuit (example)
1.3V 1N914
Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE
5108 FHD F04
3.3K DEVICE UNDER TEST OUT CL = 30 pF CL INCLUDES JIG CAPACITANCE
5108 FHD F05
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer. (3) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V. (5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V. (6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) For load and reference points, see Fig. 1 (8) For load and reference points, see Fig. 2
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Doc. No. 1019, Rev. A
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