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Part: CAT28HT256-20
Category:
Memory
-> ROM
-> EEPROM
Description: Parallel EePROM, High Temp, 256Kb
Company: Catalyst Semiconductor
Datasheet: Download CAT28HT256-20 datasheet File size : 359 kB
Request For quote: Find where to buy CAT28HT256-20
Datasheet text preview:
Advanced
CAT28HT256
256K-Bit CMOS PARALLEL E PROM
2
Extended Temperature: 170°C
FEATURES
s Fast Read Access Times: 200/250 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation:
Active: 30 mA Max. Standby: 150 µA Max.
s Simple Write Operation:
1 to 64 Bytes in 10ms Page Load Timer
s End of Write Detection:
On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
Toggle Bit DATA Polling
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention
10ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28HT256 is a fast, low power, 5V-only CMOS parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28HT256 features hardware and software write protection as well as an internal Error Correction Code (ECC) for extremely high reliability. The CAT28HT256 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin Ceramic DIP package.
BLOCK DIAGRAM
A6A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
5096 FHD F02
I/O0I/O7
A0A5
ADDR. BUFFER & LATCHES
© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
8-91
CAT28HT256
Advanced
PIN CONFIGURATION
CERDIP Package (D)
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
5096 FHD F01
PIN FUNCTIONS
Pin Name A0A14 I/O0I/O7 CE OE WE VCC VSS NC Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable 5V Supply Ground No Connect
RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(2) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 104 or 105 100 2000 100 Max. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
Stock No. 21065-03 2/98
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Advanced
CAT28HT256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ 55°C to +150°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(1) .. 2.0V to +VCC + 2.0V VCC with Respect to Ground ...... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .. 1.0W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(2) ...... 100 mA D.C. OPERATING CHARACTERISTICS
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
VCC = 5V ±10%, unless otherwise specified. (Temperature 0°C to 170°C) Limits Symbol ICC ICCC(3) ISB ISBC(4) ILI ILO VIH(4) VIL(3) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 3.5 10 10 2 0.3 2.4 0.4 Min. Typ. Max. 30 25 1 300 20 20 VCC +0.3 0.8 Units mA mA mA µA µA µA V V V V V IOH = 400µA IOL = 2.1mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = OE = VILC, f = 1/tRC min, All I/O's Open CE = VIH, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
Note: (1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) VILC = 0.3V to +0.3V. (4) VIHC = VCC 0.3V to VCC +0.3V.
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CAT28HT256
Advanced
A.C. CHARACTERISTICS, Read Cycle VCC = 5V ±10%, unless otherwise specified. (Temperature 0°C to 170°C) 28HT256-20 Symbol t RC tCE t AA t OE tLZ(1) tOLZ(1) tHZ(1)(4) tOHZ(1)(4) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. Max. 200 200 200 80 0 0 50 50 28HT256-25 Min. 250 250 250 100 Max. Units ns ns ns ns ns ns ns ns ns
A.C. CHARACTERISTICS, Write Cycle VCC = 5V ±10%, unless otherwise specified. (Temperature 0°C to 170°C) 28HT256-20 Symbol tWC tAS tAH tCS tCH tCW(2) tOES tOEH tWP(2) tDS tDH tINIT(1) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up 0 75 0 0 100 0 0 100 50 10 5 0.1 10 100 Min. Max. 10 0 75 0 0 100 0 0 100 50 10 5 0.1 10 100 28HT256-25 Min. Max. Units 10 ms ns ns ns ns ns ns ns ns ns ns ms µs
tBLC(1)(3) Byte Load Cycle Time
Note: (1) This parameter is tested intitially and after a design or process change that affects the parameter.. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Stock No. 21065-03 2/98
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Advanced
CAT28HT256
DEVICE OPERATION
Read Data stored in the CAT28HT256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Figure 1. A.C. Testing Input/Output Waveform(1)
2.4 V INPUT PULSE LEVELS 0.45 V
Note: (1) Input rise and fall times (10% and 90%) < 10 ns.
Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms.
2.0 V REFERENCE POINTS 0.8 V
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V 1N914
3.3K DEVICE UNDER TEST OUT CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5096 FHD F04
Figure 3. Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tLZ tOLZ DATA OUT HIGH-Z tOH DATA VALID tAA tOHZ tHZ DATA VALID
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Stock No. 21065-03 2/98
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