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Part: CAT28LV256-35
Category:
Memory
-> ROM
-> EEPROM
Description: Parallel EePROM, Low Voltage, 256Kb
Company: Catalyst Semiconductor
Datasheet: Download CAT28LV256-35 datasheet File size : 359 kB
Request For quote: Find where to buy CAT28LV256-35
Datasheet text preview:
CAT28LV256
256K-Bit CMOS PARALLEL E2PROM FEATURES
s 3.0V to 3.6V Supply s Read Access Times: 200/250/300 ns s Low Power CMOS Dissipation: s CMOS and TTL Compatible I/O s Automatic Page Write Operation:
Active: 15 mA Max. Standby: 150 µA Max.
s Simple Write Operation:
1 to 64 Bytes in 10ms Page Load Timer
s End of Write Detection:
On-Chip Address and Data Latches Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
Toggle Bit DATA Polling DATA
s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention
10ms Max.
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage CMOS Parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28LV256 features hardware and software write protection. The CAT28LV256 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages.
BLOCK DIAGRAM
A6A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
28LV256 F01
I/O0I/O7
A0A5
ADDR. BUFFER & LATCHES
© 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 25040-00 4/01 P-1
CAT28LV256
PIN CONFIGURATION
DIP Package (P) PLCC Package (N)
A14 NC VCC WE A13
29 28 27 26 TOP VIEW 25 24 23 22
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9
A7 A12
4 3 2 1 32 31 30 A8 A9 A11 NC OE A10 CE I/O7 I/O6
10 11 12
13 21 14 15 16 17 18 19 20
I/O1 I/O2
VSS NC I/O3 I/O4 I/O5
28LV256 F02
TSOP Top View (8mm X 13.4mm) (T13)
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
28LV256 F03
PIN FUNCTIONS
Pin Name A0A14 I/O0I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 3.0 to 3.6 V Supply Ground No Connect
Doc. No. 25040-00 4/01 P-1
2
CAT28LV256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ 55°C to +125°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(2) .. 2.0V to +VCC + 2.0V VCC with Respect to Ground ...... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .. 1.0W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(3) ...... 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(1)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 100,000 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
TDR(1) VZAP
(1)
ILTH(1)(4)
CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CI/O(1) CIN(1) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
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Doc. No. 25040-00 4/01 P-1
CAT28LV256
D.C. OPERATING CHARACTERISTICS VCC = 3.0V to 3.6V, unless otherwise specified Limits Symbol ICC ISBC(2) ILI ILO VIH(2) VIL VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 2 1 5 2 0.3 2 0.3 Min. Typ. Max. 15 150 1 5 VCC +0.3 0.6 Units mA µA µA µA V V V V V IOH = 100µA IOL = 1.0mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
A.C. CHARACTERISTICS, Read Cycle VCC = 3.0V to 3.6V, unless otherwise specified 28LV256-20 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(3) tOHZ(1)(3) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OE Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. 200 200 200 80 0 0 55 55 0 Max. 28LV256-25 Min. 250 250 250 100 0 0 60 60 Max. 28LV256-30 Min. 300 300 300 110 Max. Units ns ns ns ns ns ns ns ns ns
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) VIHC = VCC 0.3V to VCC +0.3V. (3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 25040-00 4/01 P-1
4
CAT28LV256
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V INPUT PULSE LEVELS 0.0 V 0.6 V
28LV256 F04
2.0 V REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
1.8K DEVICE UNDER TEST 1.3K OUTPUT CL = 100 pF
CL INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle VCC = 3.0V to 3.6V, unless otherwise specified
28LV256-20 Symbol tWC tAS tAH tCS tCH tCW(3) tOES tOEH tWP(3) tDS tDH tINIT(1) tBLC(1)(4) Parameter Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up Byte Load Cycle Time 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100 Min. Max. 10
28LV256-25 Min. Max. 10 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100
28LV256-30 Min. Max. Units 10 0 100 0 0 150 0 0 150 50 0 5 0.15 10 100 ms ns ns ns ns ns ns ns ns ns ns ms µs
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Input rise and fall times (10% and 90%) < 10 ns. (3) A write pulse of less than 20ns duration will not initiate a write cycle. (4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer.
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Doc. No. 25040-00 4/01 P-1
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