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Part: CAT28LV64
Category:
Memory
-> ROM
-> EEPROM
-> 64 Kb
Description: Parallel EePROM, Low Voltage, 64Kb
Company: Catalyst Semiconductor
Datasheet: Download CAT28LV64 datasheet File size : 359 kB
Request For quote: Find where to buy CAT28LV64
Datasheet text preview:
CAT28LV64
64K-Bit CMOS PARALLEL EEPROM FEATURES
s 3.0V to 3.6 V Supply s Read access times: s CMOS and TTL compatible I/O s Automatic page write operation:
150/200/250ns
s Low power CMOS dissipation:
1 to 32 bytes in 5ms Page load timer
s End of write detection:
Active: 8 mA max. Standby: 100 µA max.
s Simple write operation:
Toggle bit DATA polling DATA
s Hardware and software write protection s 100,000 program/erase cycles s 100 year data retention
On-chip address and data latches Self-timed write cycle with auto-clear
s Fast write cycle time:
5ms max.
s Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS parallel EEPROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the selftimed write cycle. Additionally, the CAT28LV64 features hardware and software write protection. The CAT28LV64 is manufactured using Catalyst's advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.
BLOCK DIAGRAM
A5A12 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER
VCC
HIGH VOLTAGE GENERATOR
CE OE WE
CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER
5094 FHD F02
I/O0I/O7
A0A4
ADDR. BUFFER & LATCHES
© 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 1010, Rev. B
CAT28LV64
Preliminary
PIN CONFIGURATION
DIP Package (P)
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
SOIC Package (J, K)
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
PLCC Package (N)
A12 NC NC VCC WE NC A7
OE A11 A9 A8 NC WE VCC NC A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14
TSOP Top View (8mm x 13.4mm) (T13)
28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 TOP VIEW 29 28 27 26 25 24 23 22 A8 A9 A11 NC OE A10 CE I/O7 I/O6
13 21 14 15 16 17 18 19 20
28LV64 F03
I/O1
I/O2 VSS NC
I/O3
PIN FUNCTIONS
Pin Name A0A12 I/O0I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE V CC VSS NC Function Write Enable 3.0 to 3.6 V Supply Ground No Connect
Doc. No. 1010, Rev. B
I/O4 I/O5
2
Preliminary
CAT28LV64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ........ 55°C to +125°C Storage Temperature ..... 65°C to +150°C Voltage on Any Pin with Respect to Ground(2) .. 2.0V to +VCC + 2.0V VCC with Respect to Ground ...... 2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) .. 1.0W Lead Soldering Temperature (10 secs) ... 300°C Output Short Circuit Current(3) ...... 100 mA RELIABILITY CHARACTERISTICS Symbol NEND
(1)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Min. 105 100 2000 100
Max.
Units Cycles/Byte Years Volts mA
Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
T DR (1) VZAP
(1)
ILTH(1)(4)
MODE SELECTION Mode Read Byte Write (WE Controlled) Byte Write (CE Controlled) Standby, and Write Inhibit Read and Write Inhibit H X CE L L L X H WE H OE L H H X H I/O DOUT DIN DIN High-Z High-Z Power ACTIVE ACTIVE ACTIVE STANDBY ACTIVE
CAPACITANCE TA = 25°C, f = 1.0 MHz Symbol CI/O
(1)
Test Input/Output Capacitance Input Capacitance
Max. 10 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
CIN(1)
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC +1V.
3
Doc. No. 1010, Rev. B
CAT28LV64
D.C. OPERATING CHARACTERISTICS Vcc = 3.0V to 3.6V, unless otherwise specified.
Preliminary
Limits Symbol ICC ISBC(3) ILI ILO VIH(3) VIL VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Write Inhibit Voltage 2 1 5 2 0.3 2 0.3 Min. Typ. Max. 8 100 1 5 VCC +0.3 0.6 Units mA µA µA µA V V V V V IOH = 100µA IOL = 1.0mA Test Conditions CE = OE = VIL, f = 1/tRC min, All I/O's Open CE = VIHC, All I/O's Open VIN = GND to VCC VOUT = GND to VCC, CE = VIH
A.C. CHARACTERISTICS, Read Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV64-15 Symbol tRC tCE tAA tOE tLZ(1) tOLZ(1) tHZ(1)(2) tOHZ(1)(2) tOH(1) Parameter Read Cycle Time CE Access Time Address Access Time OEAccess Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change 0 0 0 50 50 0 Min. 150 150 150 70 0 0 50 50 0 0 55 55 Max. 28LV64-20 Min. 200 200 200 80 0 Max. 28LV64-25 Min. 250 250 250 100 Max. Units ns ns ns ns ns ns ns ns ns
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) VIHC = VCC 0.3V to VCC +0.3V.
Doc. No. 1010, Rev. B
4
Preliminary
Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V INPUT PULSE LEVELS 0.0 V 0.6 V 2.0 V REFERENCE POINTS
CAT28LV64
28LV64 F04
Figure 2. A.C. Testing Load Circuit (example)
Vcc 1.8 K DEVICE UNDER TEST OUTPUT 1. 3K CL= 100 pF
CL INCLUDES JIG CAPACITANCE
28LV64 F05
A.C. CHARACTERISTICS, Write Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV64-15 Symbol t WC tAS tAH tCS tCH tCW(2) t OES tOEH tWP
(2)
28LV64-20 Min Max 5 0 100 0 0 150 10 10 150 100 0
28LV64-25 Min Max 5 0 100 0 0 150 10 10 150 100 0 Units ms ns ns ns ns ns ns ns ns ns ns 10 100 ms µs
Parameter Write Cycle Time Address Setup Time0 Address Hold Time CE Setup Time CE Hold Time CE Pulse Time OE Setup Time OE Hold Time WE Pulse Width Data Setup Time Data Hold Time Write Inhibit Period After Power-up Byte Load Cycle Time
Min
Max 5
0 100 0 0 110 0 0 110 60 0 5 0.05 10 100
tDS tDH tINIT(1) tBLC(1)(3)
5 0.1
10 100
5 0.1
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Input rise and fall times (10% and 90%) < 10 ns.
5
Doc. No. 1010, Rev. B
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