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Part: CAT515JI-TE13
Category:
Analog & Mixed-Signal Processing
Description: 8-bit Quad Digital Pot
Company: Catalyst Semiconductor
Datasheet: Download CAT515JI-TE13 datasheet File size : 32 kB
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Datasheet text preview:
CAT525
Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications
FEATURES
s Four 8-bit DPPs configured as programmable
APPLICATIONS
s Automated product calibration s Remote control adjustment of equipment s Offset, gain and zero adjustments in
voltage sources in DAC-like applications
s Independent reference inputs s Buffered wiper outputs s Non-volatile NVRAM memory wiper storage s Output voltage range includes both supply rails s 4 independently addressable buffered
self-calibrating and adaptive control systems
s Tamper-proof calibrations s DAC (with memory) substitute
output wipers
s 1 LSB accuracy, high resolution s Serial Microwire-like interface s Single supply operation: 2.7V - 5.5V s Setting read-back without effecting outputs
DESCRIPTION
The CAT525 is a quad 8-bit digitally programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The CAT525 offers four independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to FUNCTIONAL DIAGRAM
V REF H1 V REF H3 V REF H4 19 V REF H2 2 1 20
test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP's output. Control of the CAT525 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the CAT525's TriStated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. The CAT525 is available in the 0°C to 70°C commercial and -40°C to 85°C industrial operating temperature ranges and offered in 20-pin plastic DIP and surface mount packages. PIN CONFIGURATION
DIP Package (P) SOIC Package (J)
VREFH2 VREF H1 VDD CLK RDY/BSY CS DI DO PROG GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 VREF H3 VREF H4 VOUT1 VOUT2 VOUT3 VOUT4 VREFL4 VREFL3 VREFL2 VREF L1
RDY/BSY
5
+
PROG 9 PROGRAM CONTROL
18
V UT1 O
VREFH2 VREF H1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VREF H3 VREF H4 VOUT1 VOUT2 VOUT3 VOUT4 VREFL4 VREFL3 VREFL2 VREF L1
CLK
4 DATA CONTROLLER
WIPER CONTROL REGISTERS AND NVRAM
+
17
V UT2 O
VDD CLK
+
16
CS
6
V UT3 O
RDY/BSY CS
DI
7
+
15
V UT4 O
CAT525
CAT525
15 14 13 12 11
DI DO
28k (ea)
H.V. CHARGE PUMP
SERIAL DATA OUTPUT REGISTER 8
DO
PROG GND
CAT525
11
12
13
14 VREFL4
VREFL2 V REFL1
VREFL3
© 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 2001, Rev. B
CAT525
ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ..... -0.5V to +7V Inputs CLK to GND .... -0.5V to VDD +0.5V CS to GND ...... -0.5V to VDD +0.5V DI to GND ....... -0.5V to VDD +0.5V RDY/BSY to GND .......... -0.5V to VDD +0.5V PROG to GND ...... -0.5V to VDD +0.5V VREFH to GND ...... -0.5V to VDD +0.5V VREFL to GND ....... -0.5V to VDD +0.5V Outputs D0 to GND ....... -0.5V to VDD +0.5V VOUT 1 4 to GND .......... -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol
VZAP(1) ILTH(1)(2)
Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0°C to +70°C Industrial (`I' suffix) ...... -40°C to +85°C Junction Temperature .... +150°C Storage Temperature ...... -65°C to +150°C Lead Soldering (10 sec max) .. +300°C
* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.
Parameter
ESD Susceptibility Latch-Up
Min
2000 100
Max
Units
Volts mA
Test Method
MIL-STD-883, Test Method 3015 JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from 1V to VCC + 1V.
POWER SUPPLY Symbol Parameter IDD1 IDD2 Supply Current (Read) Supply Current (Write) Conditions Normal Operating Programming, VDD = 5V VDD = 3V VDD Operating Voltage Range Min -- -- -- 2.7 Typ 400 1600 1000 -- Max 600 2500 1600 5.5 Units µA µA µA V
LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min -- -- 2 0 Typ -- -- -- -- Max 10 -10 V DD 0.8 Units µA µA V V
LOGIC OUTPUTS Symbol Parameter VOH VIL High Level Output Voltage Low Level Output Voltage Conditions IOH = -40µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V Min VDD -0.3 -- -- Typ -- -- -- Max -- 0.4 0.4 Units V V V
Doc. No. 2001, Rev. B
2
CAT525
POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT I OUT TC RPOT TCRATIO RISO VN CH/CL fc Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Ratiometric TC Isolation Resistance Noise Potentiometer Capacitances Frequency Response Passive Attenuator 8/8 300 2.7 OV 0.4 0.5 0.25 1 0.5 10 3 -- Conditions Min Typ 28 +0.5 +1 +15 V DD VDD - 2.7 Max Units k % % V V % LSB LSB mA ppm/°C ppm/°C nV/Hz pF MHz
AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital
tCSMIN t CSS tCSH t DIS tDIH t DO1 t DO0 tHZ t LZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency DPP Settling Time to 1 LSB 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- 3 6 -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 10 10 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz µs µs
Parameter
Conditions
Min
Typ
Max
Units
CL=100pF, see note 1
Analog
tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 2001, Rev. B
TIMING MIN/MAX FROM TO
CAT525
A. C. TIMING DIAGRAM
Doc. No. 2001, Rev. B
to 1 2 3 4 5
PARAM NAME
t CLK H t CLK H Rising CLK edge to falling CLK edge
Min
CLK t CLK L Falling CLK edge to CLK rising edge t CSH t CLK L t CSS t CSH Falling CLK edge for last data bit (DI) to falling CS edge Rising CS edge to next rising CLK edge Min Min
t CSS
Min
CS t CSMIN t CSMIN Falling CS edge to rising CS edge t DIS Data valid to first rising CLK edge after CS = high Min
Min
t DIS
DI t DIH t DIH t DO0 t LZ t DO0 Rising CLK edge to end of data valid Min
4
t HZ t DO1 t PS t PROG t BUSY 1 2 3 4 5
Rising CLK edge to D0 = low Rising CS edge to D0 becoming high low impedance (active output)
Max (Max)
t LZ
DO t DO1 t HZ Rising CLK edge to D0 = high Falling CS edge to D0 becoming high impedance (Tri-State) t PS Max (Max)
PROG
Rising PROG edge to next rising CLK edge t PROG Rising PROG edge to falling PROG edge t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge
Min Min
RDY/BSY Max
to
CAT525
PIN DESCRIPTION Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CDPP/DPP addressing is as follows: Function
Maximum DPP 2 output voltage Maximum DPP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin Non-volatile Memory Programming Enable Input Power supply ground Minimum DPP 1 output voltage Minimum DPP 2 output voltage Minimum DPP 3 output voltage Minimum DPP 4 output voltage DPP 4 output DPP 3 output DPP 2 output DPP 1 output Maximum DPP 4 output voltage Maximum DPP 3 output voltage
Name
VREFH2 VREFH1 VDD CLK RDY/BSY CS DI DO PROG GND VREFL1 VREFL2 VREFL3 VREFL4 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3
DPP OUTPUT VOUT1 VOUT2 VOUT3 VOUT4
A0 0 1 0 1
A1 0 0 1 1
DEVICE OPERATION The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high
5
impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT525's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT525's clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT525's internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock.
Doc. No. 2001, Rev. B
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