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Part: CAT521JI-TE13

Category:
 Analog & Mixed-Signal Processing
   -> Potentiometers

Description: 8-bit Digital Pot With Independent Reference Input

Company: Catalyst Semiconductor

Datasheet: Download CAT521JI-TE13 datasheet     File size : 31 kB

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Datasheet text preview:
CAT521
Configured Digitally Programmable Potentiometer (DPPTM): Programmable Voltage Applications

FEATURES
s 8-bit DPP configured as a programmable

APPLICATIONS
s Automated product calibration s Remote control adjustment of equipment s Offset, gain and zero adjustments in

voltage source in DAC-like applications
s Buffered wiper output s Non-volatile NVRAM memory wiper storage s Output voltage range includes both supply rails s 1 LSB accuracy, high resolution s Serial Microwire-like interface s Single supply operation: 2.7V - 5.5V s Setting read-back without effecting outputs

self-calibrating and adaptive control systems
s Tamper-proof calibrations s DAC (with memory) substitute

DESCRIPTION
T h e CAT521 is a 8-bit digitally-programmable potentiometer (DPPTM) configured for programmable voltage and DAC-like applications. Intended for final c a l i b r a t i o n of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. The programmable DPP has an output voltage range which includes both supply rails. The wiper is buffered by a rail to rail op amp. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be dithered to test new output values without effecting the stored FUNCTIONAL DIAGRAM
RDY/BSY V DD
V REFH

settings and stored settings can be read back without disturbing the DPP's output. The CAT521 is controlled with a simple 3-wire, Microwirelike serial interface. A Chip Select pin allows several d e v i c e s to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the CAT521 Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The CAT521 is available in 0°C to 70°C commercial and -40°C to 85°C industrial operating temperature ranges. Both 14-pin plastic DIP and surface mount packages are available.

PIN CONFIGURATION
DIP Package (P)
VDD CLK 1 2
CAT521

SOIC Package (J)
VDD CLK RDY/BSY CS DI DO PROG 1 2
CAT521

3

1

14

PROG

7

PROGRAM CONTROL

14 13 12 11 10 9 8

VREFH NC VOUT NC NC VREFL GND

14 13 12 11 10 9 8

VREFH NC VOUT NC NC VREFL GND

DI

5 WIPER CONTROL REGISTER AND NVRAM

RDY/BSY CS
28k

3 4 5 6 7

3 4 5 6 7

CLK

2

SERIAL CONTROL

CS

4

+

12

V OUT

DI DO PROG

SERIAL DATA OUTPUT REGISTER

6 DO

CAT521
8
GND

9
VREFL

© 2002 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice

1

Doc. No. 2003, Rev. C

CAT521
ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ..... -0.5V to +7V Inputs CLK to GND .... -0.5V to VDD +0.5V CS to GND ...... -0.5V to VDD +0.5V DI to GND ....... -0.5V to VDD +0.5V RDY/BSY to GND .......... -0.5V to VDD +0.5V PROG to GND ...... -0.5V to VDD +0.5V VREFH to GND ...... -0.5V to VDD +0.5V VREFL to GND ....... -0.5V to VDD +0.5V Outputs D0 to GND ....... -0.5V to VDD +0.5V VOUT 1­ 4 to GND .......... -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol
VZAP(1) ILTH(1)(2)

Operating Ambient Temperature Commercial (`C' or Blank suffix) ...... 0°C to +70°C Industrial (`I' suffix) ...... -40°C to +85°C Junction Temperature .... +150°C Storage Temperature ...... -65°C to +150°C Lead Soldering (10 sec max) .. +300°C
* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.

Parameter
ESD Susceptibility Latch-Up

Min
2000 100

Max

Units
Volts mA

Test Method
MIL-STD-883, Test Method 3015 JEDEC Standard 17

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from ­1V to VCC + 1V.

POWER SUPPLY Symbol Parameter I DD1 I DD2 Supply Current (Read) Supply Current (Write) Conditions Normal Operating Programming, VDD = 5V VDD = 3V V DD Operating Voltage Range Min -- -- -- 2.7 Typ 400 1600 1000 -- Max 600 2500 1600 5.5 Units µA µA µA V

LOGIC INPUTS Symbol IIH IIL VIH VIL Parameter Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage Conditions VIN = VDD VIN = 0V Min -- -- 2 0 Typ -- -- -- -- Max 10 -10 VDD 0.8 Units µA µA V V

LOGIC OUTPUTS Symbol Parameter VOH VIL High Level Output Voltage Low Level Output Voltage Conditions IOH = -40µA IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V Min VDD -0.3 -- -- Typ -- -- -- Max -- 0.4 0.4 Units V V V

Doc. No. 2003, Rev. C

2

CAT521

POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Potentiometer Resistance RPOT to RPOT Match Pot Resistance Tolerance Voltage on VREFH pin Voltage on VREFL pin Resolution INL DNL ROUT I OUT TC RPOT TCRATIO RISO VN CH/CL fc Integral Linearity Error Differential Linearity Error Buffer Output Resistance Buffer Output Current TC of Pot Resistance Ratiometric TC Isolation Resistance Noise Potentiometer Capacitances Frequency Response Passive Attenuator 8/8 300 2.7 OV 0.4 0.5 0.25 1 0.5 10 3 -- Conditions Min Typ 28 +0.5 +1 +15 V DD VDD - 2.7 Max Units k % % V V % LSB LSB mA ppm/°C ppm/°C nV/Hz pF MHz

AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital
tCSMIN t CSS tCSH t DIS tDIH t DO1 t DO0 tHZ t LZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency DPP Settling Time to 1 LSB 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- 3 6 -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 10 10 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz µs µs

Parameter

Conditions

Min

Typ

Max

Units

CL=100pF, see note 1

Analog
tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V

NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested.

3

Doc. No. 2003, Rev. C

CAT521
A. C. TIMING DIAGRAM

to

1

2

3

4

5

t CLK H CLK

t CSS CS

t CLK L

t CSH

t CSMIN

t DIS DI t DIH

t LZ DO

t DO0

t HZ t DO1

PROG t PS t PROG RDY/BSY t BUSY

to

1

2

3

4

5

Doc. No. 2003, Rev. C

4

CAT521
PIN DESCRIPTION Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14

DPP addressing is as follows: Function
Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DAC output voltage No Connect No Connect DPP output No Connect Maximum DPP 1 output voltage

Name
VDD CLK RDY/BSY CS DI DO PROG GND VREFL NC NC VOUT NC VREFH

DPP OUTPUT VOUT

A0 1

A1 0

DEVICE OPERATION The CAT521 is a single 8-bit configured digitally programmable potentiometer (DPPTM) whose output can be programmed to any one of 256 individual voltage steps. Once programmed, the output setting is retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPP returns to the setting stored in non-volatile memory. The DPP can be written to and read from without effecting the output voltage during the read or write cycle. The output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT521 employs a 3 wire, Microwire-like serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DPP address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use.

CHIP SELECT Chip Select (CS) enables and disables the CAT521's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control register will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT521 clock controls both data flow in and out of the device and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. No clock is necessary upon system power-up. The CAT521 internal power-on reset circuitry loads data from non-volatile memory to the DPP without using the external clock.

5

Doc. No. 2003, Rev. C




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