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Part: CX3000
Category:
ASICs
-> Gate Array
Description: 0.35u CMOS Gate Array Family
Company: Chip Express Corporation
Datasheet: Download CX3000 datasheet File size : 1379 kB
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Datasheet text preview:
X3000 0.35µ CMOS Gate Array Family
C
Introduction
Features
Density Power Voltage · 40K to 1.5M logic gates (2 input NAND gate equivalent) · Low power dissipation 0.3µW/MHz/Gate @3.3V · Solely 5V, solely 3.3V, mixed 3.3V/5V
The CX3000 0.35µ CMOS technology is a high performance gate array product family, offering rapid prototype turnaround time and low-cost, high-volume production. These benefits are achieved using Chip Express' unique architecture and manufacturing through our world-class foundry partner, Chartered Semiconductor (Singapore). The CX3000 technology features high density (10K gates/mm2) and logic capacity of up to 1.5M gates. This high density results from utilizing a fourlayer metal interconnection, enabling competitive prices for high-volume production. Additionally, the CX3000 technology features extremely low power dissipation of 0.3µW/MHz/gate, and a unique voltage flexibility utilizing a dual-oxide process that allows operating with solely 5V Vcc. This product family offers up to four embedded analog PLLs.
Performance · High speed 8x8 multiplier with 5.6ns cycle (one stage pipeline) I/Os · Rich I/O libraries (2308 cells) · Up to 592 I/Os · All I/O pads can be used for power and/or ground · 5V drive or 3.3V operation with 5V tolerance, mixed 3.3V & 5V · 3.3V PCI-compliant at 66MHz · Differential input support modes such as GTL and USB · Embedded synchronous single or dual-port SRAM or ROM · Configurable 8K to 416K bits · High speed-360MHz SRAM @ 3.3V for worst case
Embedded Configurable Memory
An inherent feature of CX3000 technology is the availability of high performance configurable embedded memory. The CX 3000 product family offers synchronous memory ranging from 8K to 416K bits of single-port or dual-port SRAM or ROM with up to 52 different block configurations. The high-speed programmable SRAM is capable of operating at speeds in excess of 360MHz @ 3.3V for worst case (single-port or dual-port). The CX3000 technology also includes a BIST (Built-In Self Test) that enables the testing of the embedded memory and ensures high fault coverage.
Memory
Analog PLL · 3 or 4 APLLs with clock synchronization and multiplication of 200MHz @ 3.3V ATPG · Built-in scan capability with minimum impact on performance and 1-2% utilization impact · DRC utilities (Check_all) · Clock Tree Synthesis (CTS) with <500ps clock-skew · Automatic cross-talk handling · BIST for memory testing
CAE Tools
Device Outline
Power Lines I/Os
Core
Analog PLLs
Memory Blocks
ASIC Services
Laser Prototypes - CX3001 One-day turnaround time is available for LPGA (Laser Programmable Gate Array) prototypes using the Chip Express QuICk® laser micro-machining system, which rapidly customizes one die at a time. Low-Mid Volume - CX3001 One-week turnaround time is available for low volume gate array production with the proprietary OneMask® technology. Customization is done using single mask, single wafer processing. One-month lead-time for mid-volume production is available with the TwoMaskTM technology. No conversion or additional engineering development is required after the prototyping phase is complete. High Volume Production - CX3002 Two-month lead-time for smooth migration to a smaller die size for price reduction is available for high volume production. This is accomplished using the HardArrayTM technology with a multi-mask process that provides high gate utilization. RTL Sign-off Chip Express has developed an RTL sign-off flow to further shorten time-to-market, where instead of submitting the gate-level netlist, the designer can now interface at a higher level of abstraction. Conversion Chip Express offers conversion of FPGA (Actel, Altera, Xilinx) or gate array designs from other ASIC vendors (LSI Logic, VLSI) to Chip Express libraries. Functionality of converted designs is maintained. Furthermore, the CX3000 technology features the unique capability of converting 5V gate array designs from older process geometries to 0.35µ technology for reduced production costs.
Design Kits
CX3000 libraries for popular EDA design environments are available at no charge at the Chip Express web-site.
Tool Format Vendor Platform Verilog/ Synopsys VHDL Sun/HP Sun/PC Sun/HP
Design Services
Chip Express provides the following optional design services: IP Cores With its CorExpressTM program, Chip Express has partnered with leading core suppliers like Mentor Graphics/ Inventra Group, Sierra Research and Virtual Chips to provide system designers with preverified IP blocks (PCI, micro-controllers, ethernet controllers, bus interface, etc.). In addition, Chip Express has access to some Lucent IP cores. ATPG Recognizing that testability is a critical issue in today's large and complex ASIC designs, Chip Express offers ATPG implementation that is based on full-scan fault coverage methodology. This is accomplished in the CX3000 technology with minimum performance impact and only 1-2% utilization impact. This service can be provided as an add-on at the end of the design.
Synthesis Design Compiler
Leonardo Verilog/ Exemplar VHDL BuildGate Verilog/ VHDL/ EDIF Simulation Verilog XL VSS Ambit
Verilog Cadence Vital95 Synopsys VHDL Mentor Mentor
Sun/HP Sun/HP Sun/HP PC - NT Sun/HP S un Sun/HP
Modeltech Vital95 VHDL Modeltech Vital95 VHDL Static Timing ATPG* Design Time
Verilog/ Synopsys VHDL SynTest
Turbocheck Verilog Test Compiler
Verilog/ Synopsys VHDL
* Turbocheck is available upon special request Consult factory for availability
Input, Output & Bi-directional Cells T
he libraries for the CX3000 technology contain a large selection of input, output and bi-directional cells facilitating a wide range of designs. Input cells can be personalized with internal pull-up or pull-down resistors and with or without hysteresis. If required, outputs can be connected in parallel to provide increased drive capability. There can be several sections of 3.3V and 5V I/O interfaces. The CX3000 technology features PCI compliance and differential input support such as GTL and USB.
Mixed Voltage Features
Using the dual-oxide process the CX3000 product family enables mixed 3.3V/5V I/Os and 5V tolerance. The CX3000 technology core device operates at 3.3V. The I/O macros can be 3.3V I/O or 5V I/O. When 3.3V supply is not possible, the Chip Express special Voltage Regulator is used. This Special Circuit enables 5V-based designs to be implemented in CX3000 devices.
LPGA Design Flow*
Functional Simulation RTL VHDL/Verilog
Synthesis libraray
Gate Level Netlist
Synthesis
Static Timing Analysis
Vectors: YTV, CTV
Gate Level Simulation
Simulation librar y
Pre Layout Verification (check_all)
Package File
Placement
Scan Insertion & ATPG**
SDF/ Delay File
Routing
Post-layout Netlist
Post-Layout Verification (Check_all) Sign-Off & Customer Approval LPGA Prototypes (1 day)
Design Modification
HW Verification = Supplied by Chip Express
Low Volume (1 week)
Mid Volume (1 month)
High Volume (2 months)
= Supplied by Customer ** Optional
* For a detailed Design Flow please check the CX Design Manual
roduct Families P
The CX3000 technology is comprised of two gate array families: the CX3001, designed for fast prototyping and low volume production, implemented in three-layer metal technology, and the CX3002, aimed at cost reduction for high volume production, implemented in four-layer metal technology.
Architecture
The basic building block of the CX3000 technology is a module that is configurable to operate in a very broad range of simple and complex circuit functions and combinations. This modular structure is an innovative approach combining improved silicon utilization and low power consumption with a fastturn manufacturing capability. Each module is made up of three multiplexers and one AND gate and is logically equivalent to three or four logic gates (depending on the application).
CX3001 Family - Prototypes & Low/Mid Volume
Base Array I/Os Pads Memor y Bits No. of ations CX3041 CX3061 CX3141 CX3301 CX3551 160 208 304 424 592 178 208 304 432 608 24K 64K 96K 144K 416K 6 8 12 18 52 13K 20K 45K 100K 185K 40K 60K 140K 300K 550K Modules/ Max Logic Usable Logic Gates* 22K-32K 33K-48K 77K-112K 165K-240K 303K-440K Configur- Logic Cells Gates
CX3002 Family - High Volume Production
Base Array I/Os Pads Memor y No. of Bits ations CX3042 CX3072 CX3122 CX3182 CX3422 CX3902 100 128 160 208 304 424 108 168 224 280 408 576 808 8K 16K 24K 64K 96K 144K 416K 2 4 6 8 12 18 52 14K 24K 40K 60K 140K 300K 550K 40K 70K 120K 180K 420K 900K 1.5M Modules/ Max Logic Usable Logic Gates* 22K-32K 39K-56K 66K-96K 99K-144K 231K-336K 495K-720K 825K-1.2M Configur- Logic Cells Gates
CX31502 592
* Actual array utilization is dependent upon characteristics of the design netlist. Utilization increases accordingly with advanced process and software tools.
Operating Conditions
Characteristic Vcc Vcc Ta 3.3 V Supply Voltage 5 V Supply Voltage Ambient Temp Range Condition All Commercial Commercial Industrial Military Best 3.6 5.25 0 - 40 - 55 Nominal Worst Unit 3.3 5.0 25 25 25 3.0 4.75 70 85 125 V V
o o o
C C C
DC Characteristics
Characteristic Vol Vol Voh Voh Ioh Iol Output Voltage Low Output Voltage Low Output Voltage High Output Voltage High High Level Current Low Level Current Condition CMOS - Compatible TTL - Compatible CMOS - Compatible TTL - Compatible Value 0.3 Vcc 0.45 0.7 Vcc 2.45 As specified on individual cells As specified on individual cells Unit V V V V A A
Package Support
Type CPGA CerQuad CQFP PQFP* TQFP* MQUAD* EQFP* PBGA CDEBGA* EBGA* Cavity down * Consult factory for prototype package availability Package Name Ceramic Pin Grid Array Ceramic Quad Pack Ceramic Quad Flat Pack Plastic Quad Flat Pack Thin Quad Flat Pack Metal Quad Flat Pack Enhanced Quad Flat Pack Plastic Ball Grid Array (cavity up) Cavity Down Enhanced Ball Grid Array Enhanced Ball Grid Array (cavity down) Pins 100, 120,132,144, 180, 208, 224, 225, 256, 299, 391 100, 120, 128, 144, 160, 176, 208, 240, 256, 304 208, 304 100, 120, 128, 144, 160, 208, 240, 304 100, 120, 128, 144, 160, 176, 208, 256 100, 128, 144, 160, 208, 240, 304 144, 160, 176, 208 225, 256, 272, 352, 388, 420, 456, 493 256, 352, 420, 432 256, 352,420,432
Chip Express products are protected by one or more of the following U.S. patents: 4,875,971;4,924,287;4,933,738;4,960,729;5,111,273;5,138,194;5,260,597;5,329,152. This information is subject to change without notice. CX3000, HardArray, OneMask, and Quick System are trademarks and registered trademarks of Chip Express. Other companies and their products mentioned are trademarked by their respective companies. Preliminary data subject to change. Copyright 1998 Chip Express August 1998.
C hip Express Corporation 2323 Owen Street, Santa Clara, California 95054 Tel: (408) 988-2445, Fax: (408) 988-2449 E-mail: moreinfo@chipx.com
www.chipexpress.com
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