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Part: CX28398

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Company: Conexant Systems, Inc.

Datasheet: Download CX28398 datasheet     File size : 1379 kB

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CX28394/28395/28398
Quad/x16/Octal--T1/E1/J1 Framers
The CX28394/28395/28398 is a family of multiple framers for T1/E1/J1 and Integrated Service Digital Network (ISDN) primary rate interfaces operating at 1.544 Mbps or 2.048 Mbps. All framers are totally independent, and each combines a sophisticated framing synchronizer and transmit/receive slip buffers. Operations are controlled through a series of memory-mapped registers accessible via a parallel microprocessor port. Extensive register support is provided for alarm and error monitoring, signaling supervision (including ISDN D-channel/SS7 process), per-channel trunk conditioning, and Facility Data Link (FDL) maintenance. A flexible serial Time Division Multiplexed (TDM) system interface that supports bus rates from 1.536 to 8.192 MHz is featured. Extensive test and diagnostic functions include a full set of loopbacks, Pseudo Random Bit Sequence (PRBS) test pattern generation, Bit Error Rate (BER) meter, and forced error insertion.

Distinguishing Features
· · · · Up to 16 T1/E1/J1 Framers in one package Extensive support of various protocols T1: SF, ESF, SLC®96, T1DM, TTC JT(J1) E1: PCM-30, G.704, G.706, G.732, ISDN primary rate (ETS300 011, INS 500) Extracts and inserts signaling bits Dual HDLC controllers per framer for data link and LAPD/SS7 signaling Two-frame transmit and receive PCM slip buffers Separate or multiplexed system bus interfaces Parallel 8-bit microprocessor port supports Intel or Motorola buses BERT generation and counting B8ZS/HDB3/Bit 7 zero suppression (CX28394 and CX28398 only) Operates from a single +3.3 Vdc ± 5% power supply Low-power CMOS technology

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Functional Block Diagram
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Receive Dual Rail or NRZ RX Slip Buffer Receive System Bus

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ZCS* Decode

T1/E1 Receive Framer

Receive Dual Rail or NRZ

ZCS* Encode Overhead Inser tion

TX Slip Buffer T1/E1 Transmit Framer

Transmit System Bus

Applications · Multiline T1/E1 Channel Service Unit/Data Service Unit (CSU/DSU) Digital Access Cross-Connect System (DACS) T1/E1 Multiplexer (MUX) PBXs and PCM channel bank ISDN Primary Rate Access (PRA) Frame Relay Switches and Access Devices (FRADS) SONET/SDH add/drop multiplexers T3/E3 channelized access concentrators

Data Link Controllers DL1+DL2

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. . .

Framer #1

External Data Link DL3*

Framer #N Control/Status Registers Framer #N
8394-8-5_019

JTAG

Test Port * CX28394 and CX28398 only.

Motorola/Intel Processor Bus

CX28394 - 4 Frames CX28398 - 8 Frames CX28395 - 16 Frames

Data Sheet

100054E June 2000

CX28398EVM--Evaluation Module, Octal T1/E1 ISDN PRI Board
T1 or E1 Connection at DSX Levels

Quad T1/E1 LIU (CX28380) Address Bus 12 Microprocessor Data Bus 8

Quad T1/E1 LIU (CX28380)

CX28398 (Octal T1/E1 Framer)

Local PCM Highway (i.e., 2 @ 8192 kbps)
8394-8-5_012

© 1999, 2000, Conexant Systems, Inc.
All Rights Reser ved. Infor mation in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a ser vice to its customers and may be used for informational pur poses only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the infor mation and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual proper ty r ights is granted by this document. Except as provided in Conexant's Ter ms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or ser vices listed in this publication are for identification pur poses only, and may be trademarks of third par ties. Third-par ty brands and names are the proper ty of their respective owners. For additional disclaimer infor mation, please consult Conexant's Legal Infor mation posted at www.conexant.com, which is incor porated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.

100054E

Conexant

Typical Quad T1/E1 Application
T1 or E1 Connection at DSX Levels

CX28380 (Quad LIU) Address Bus 12 Microprocessor Data Bus 8 CX28394 (Octal T1/E1 Framer)

Local PCM Highway (8192 kbps)
8394-8-5_015

Typical x16 T1/E1 Application

T1 or E1 Line Interfaces, SONET/SDH Mapper or M13/E13 Mux

Address Bus 12 Microprocessor Data Bus 8 2 Chip Selects Local PCM Highways 32 at 1536 kbps to 8 at 8192 kbps)
8394-8-5_014

CX28395 ( x16 T1/E1 Framer)

CX28395 ( x16 T1/E1 Framer)

2

Ordering Information
Model Number CX28394-22 CX28398-22 CX28398-23 CX28395-19 CX28395-18 CX28398-24 BT00-D660-001 Number of Framers 4 8 8 16 16 8 Package 128-pin TQFP 208-pin PQFP 272-pin BGA 318-pin BGA 318-pin BGA 208-pin CABGA CX28398/CX28380 Evaluation Module Operating Temperature ­40 to 85 °C ­40 to 85 °C ­40 to 85 °C ­40 to 85 °C 0 to 70 °C ­40 to 85 °C

100054E

Conexant

Detailed Feature Summary
Frame Alignment · Framed formats: ­ Independent transmit and receive framing modes ­ T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1) ­ E1: FAS/MFAS/FAS+CAS/MFAS+CAS Maximum Average Reframe Time (MART) less than 50 ms Transmitter alignment modes: ­ Align to system bus data ­ Align to system bus sync ­ Align to buffer data (embedded framing) Unframed mode Out-of-Service Testing and Maintenance · Pseudo-Random Bit Sequence (PRBS): ­ Independent transmit and receive ­ 211; 215; 220; 223 patterns ­ Framed or unframed mode ­ Optional 7/14 zero limit ­ Bit Error Counter (BERR) Single error insertion: ­ PRBS error ­ Framing error ­ CRC error ­ BPV/LCV error (CX28394 and CX28398 only) ­ COFA error In-Service Performance Monitoring · · One-second timer I/O to synchronize reporting Receive error detectors with accumulators: ­ Bipolar/Line Code Violations (LCV) (CX28394 and CX28398 only) ­ Excessive Zeros (EXZ) ­ Loss of Frame (RLOF) ­ Framing Errors (FERR) ­ CRC Errors (CERR) ­ Far End Block Errors (FEBE) ­ Severely Errored Frames (SEF) ­ Change of Frame Alignment (COFA) Transmit error detectors: ­ Loss of Frame (TLOF) ­ Framing Errors (TFERR) ­ Multiframe Errors (TMERR) ­ CRC Errors (TCERR) ­ Loss of Transmit Clock (TLOC) Receive alarm detectors: ­ Alarm Indication Signal (AIS) ­ Loss of Signal (RLOS) ­ RAI/Yellow Alarm (YEL) ­ Multiframe Yellow (MYEL) ­ Lost Frame Alignment (FRED) ­ Lost Multiframe Alignment (MRED) ­ Carrier Failure Alarm (CFA) with 8:1 dual slope integration Controlled Frame Slip (RFSLIP) Uncontrolled Frame Slip (RUSLIP) Automatic and on-demand transmit alarms: ­ AIS following RLOS and/or TLOC ­ Automatic AIS clock switching ­ YEL following FRED ­ YEL following 100ms reframe timeout ­ MYEL following MRED ­ FEBE following CERR

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Signaling · · · · · · · · · · · T1: 2-, 4-, or 16-state robbed bit ABCD signaling E1: Channel Associated Signaling (CAS) Common Channel Signaling (CCS) in any time slot Per-channel receive signaling stack Signaling state change interrupt Automatic and manual signaling freeze Debounce signaling (2-bit integration) UNICODE detection Signaling reinsertion on PCM system bus Separate I/O for system bus signaling Per-channel transparent

System Bus Interface (SBI) · System bus data rates: ­ 1536 kbps (T1 without F-bits) ­ 1544 kbps (T1) ­ 2048 kbps (E1) ­ 4096 kbps (2E1) ­ 8192 kbps (4E1) Clock operation at 1x or 2x data rate Selectable I/O clock edges Master, slave, or mixed bus timing Bit and time slot frame sync offsets DS0 drop/insert indicators for external mux Embedded T1 framing transport per G.802 Receive and transmit slip buffers ­ Bypass, 2-frame, or 64-bit depth ­ Slip detection with directional status ­ Slip buffer phase status ­ Per-channel idle code insertion ­ Processor accessible data buffers Direct connection to upper layer devices: ­ Link layer: Bt8474 ­ ATM layer: CN8228 Direct connection to physical line interface ­ CX28380 Supported system bus formats: ­ ATT Concentration Highway Interface (CHI) ­ Multi-Vendor Integration Protocol (MVIP) ­ Mitel ST-bus Separate or internally multiplexed bus modes

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·

· · · · · · ·

· ·

Loopbacks · Remote loopback toward line ­ Retains BPV transparency (CX28394 and CX28398 only) Payload loopback Per-channel DS0 remote loopback Local loopback towards system ­ Framer digital loopback ­ Per-channel DS0 local loopback Inband loopback code detection/ generation Simultaneous local and remote line loopbacks

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Processor Interface · · · · · Parallel 8-bit bus Data strobes (Motorola) or address latch enable (Intel) Multiplexed or non-multiplexed address/data bus Synchronous or asynchronous data transfers Open drain interrupt output with maskable sources

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100054E

Conexant

Data Links · Two full-featured data link controllers (DL1 and DL2): ­ 64-octet transmit and receive FIFOs ­ HDLC Message Oriented Protocol (MOP) ­ Unformatted data transfer ­ Unformatted circular buffer ­ End of message/buffer interrupt ­ Near full/empty interrupts at selected depth Access any bit combination in any time slot: ­ ISDN D-channels at 16, 32, or 64 kbps ­ National/spare bits (SA-bits) in 4 kbps increments ­ CCS/SS7 ­ T1DM R-bits Access T1 F-bits in even, odd, or all frames: ­ Automatic Performance Report Message (PRM) generator ­ ESF Facility Data Link (FDL) ­ Unformatted SLC-96 overhead ­ Bit-Oriented Protocol (BOP) priority codeword generation and detection Separate I/O for external data link (DL3) on CX28394 and CX28398 devices

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100054E

Conexant




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