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Details, datasheet, quote on part number:FX802LG
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| Part: | FX802LG |
| Category: | Communication => Telephony => Codecs/Voice Codecs => PCM Line Card->Codec |
| Description: | DVSR Codec |
| Company: | Consumer Microcircuits Limited |
| Datasheet: | Download FX802LG datasheet File size : 130 kB |
| Request For quote: | Find where to buy FX802LG
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Datasheet text preview:
FX802 DVSR CODEC
SERIAL CLOCK COMMAND DATA REPLY DATA CS IRQ XTAL/ CLOCK XTAL AUDIO IN
AUDIO BYPASS
AUDIO OUT
C-BUS INTERFACE AND CONTROL LOGIC
CLOCK GENERATOR
DECODER OUTPUT
VBIAS
CONTROL PLAY COMMAND BUFFER STORE COMMAND BUFFER REGISTER STATUS REGISTER
ENCODE CLOCK
DECODE CLOCK
DATA READ COUNTER
DATA WRITE COUNTER
SPEECH PLAY COUNTERS
SPEECH STORE COUNTERS
ENCODER CLOCK DECODER CLOCK
POWER ASSESS
MOD
DEMOD
IDLE PATTERN
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
WE
CAS
RAS 1 RAS 2 RAS 3 RAS 4 A9 A8 A7 A6 A5 A4 A3/ECK A2/DCK A0/ENO (ENCODER OUT) A1/ DEI (DECODER IN)
VDD
DRAM ADDRESS LINES
VBIAS
VSS
Fig.1 FX802 DVSR Codec
Brief Description
The FX802 DVSR Codec contains: A Continuously Variable Slope Delta Modulation (CVSD) encoder and decoder. Control and timing circuitry for up to 4Mbits of external Dynamic Random Access Memory (DRAM). "C-BUS" µProcessor interface and control logic. When used with external DRAM, the FX802 has four primary functions: q Speech Storage Speech signals present at the Audio Input may be digitized by the CVSD encoder, and the resulting bit stream stored in DRAM. This process also provides readings of input power level for use by the system µController. q Speech Playback Previously digitized speech data may be read from DRAM and converted back into analogue form by the CVSD decoder. q Data Storage Digital data sent over the "C-BUS" from the system µController may be stored in DRAM. q Data Retrieval Digital data may be read from DRAM and sent over "C-BUS" to the system µController. Speech storage and playback may be performed concurrently with data storage or retrieval. The FX802 may also be used without DRAM (as a "standalone" CVSD Codec), in which case direct access is provided to the CVSD Codec digital data and clock signals. All functions are controlled by "C-BUS" commands from the system µController. The Storage, Recovery and Replay functions of the FX802 can be used for: q Answering Machine applications, where an incoming speech message is stored for later recall. q Busy Buffering, an outgoing speech message is stored temporarily until the transmit channel becomes free. q Automatic transmission of pre-recorded `Alarm' or status announcements. q Time Domain Scrambling of speech messages. q VOX control of transmitter functions. q Temporary Data Storage applications, such as buffering of over-air data transmissions. On-chip the Delta Codec is supported by input and output analogue switched-capacitor filters and audio output switching circuitry. The DRAM control and timing circuitry provides all the necessary address, control and refresh signals to interface to external DRAM. The FX802 DVSR Codec is a low-power 5-volt CMOS LSI device.
Publication D/802/4 December 1995
Pin Number Function
FX802 J 1 FX802 LG/LS Row Address Strobe 2 (RAS2): Should be connected to the Row Address Strobe input of the second 1Mbit DRAM chip (if fitted).
2
1
Row Address Strobe 1 (RAS1): Should be connected to the Row Address Strobe input of the first DRAM chip.
3
2
Write Enable (WE): The DRAM Read/Write control pin.
4
Xtal: The output of the on-chip clock oscillator. External components are required at this output when a Xtal is employed. A Xtal cannot be used with the 24-pin version.
5
3
Xtal/Clock: The input to the on-chip clock oscillator inverter. A 4.0MHz Xtal or externally derived clock should be connected here, see Figure 2. This clock provides timing for on-chip elements, filters etc. A Xtal cannot be used with the 24-pin version. Various Xtal frequencies can be used with this device, see Table 3 for the sampling clock rate variations. Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by going to a logic "0." This is a "wire-or able" output, enabling the connection of up to 8 peripherals to 1 interrupt port on the µController. The pin has a low-impedance pulldown to logic "0" when active and a high impedance when inactive. Conditions indicated by this function are: Power Reading Ready, Play Command Complete, Store Command Complete. Serial Clock: The "C-BUS," serial clock input. This clock, produced by the µController, is used for transfer timing of commands and data to and from the DVSR Codec. See Timing Diagrams and System Support Document, Document 2. The clock-rate requirements vary for differing FX802 functions. Command Data: The "C-BUS," serial data input from the µController. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams and System Support Document, Document 2.
6
4
7
5
8
6
9
7
Chip Select (CS): The "C-BUS", data transfer control function, this input is provided by the µController. Command Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagrams and System Support Document, Document 2. Reply Data: The "C-BUS," serial data output to the µController. The transmission of Reply Data bytes is synchronized to the Serial Data Clock under the control of the Chip Select input. This 3-state output is held at high impedance when not sending data to the µController. See Timing Diagrams and System Support Document, Document 2.
10
8
11
9
VBIAS: The output of the on-chip analogue circuitry bias system, held internally at VDD/2. This pin should be decoupled to VSS by a capacitor C1, See Figure 2. Audio Out: The analogue signal output.
12
10
13
11
Audio In: The audio (speech) input. The signal to this pin must be a.c. coupled by a capacitor C4 and decoupled to VSS by an HF bypass capacitor C6. For optimum noise performance this input should be driven from a source impedance of less than 100.
14
12
VSS: Negative supply rail (GND).
2
Pin Number Function
FX802 J 15 FX802 LG/LS 13 DRAM Data In/A0/ (Direct Access Encoder Out (ENO)): Connected to the DRAM data input and address line A0. With no DRAM employed this output is available (in Direct Access mode) as the Delta Encoder digital data output. Direct Access control is achieved by Control Register byte 1 bit 6.
16
14
DRAM Data Out/ A1/ (Direct Access Decoder In (DEI)): Connected to the DRAM data output and address line A1. With no DRAM employed this pin is available (in Direct Access mode) as the Delta Decoder digital data input. Direct Access control is achieved by Control Register byte 1 bit 6.
17
15
DRAM A2/ (Direct Access Decoder Clock (DCK)): DRAM address line A2. With no DRAM employed this pin is available (in Direct Access mode) as the Delta Decoder Clock input. Direct Access control is achieved by Control Register byte 1 bit 6.
18
16
DRAM A3/ (Direct Access Encoder Clock (ECK)): DRAM address line A3. With no DRAM employed this pin is available (in Direct Access mode) as the Delta Encoder Clock output. Direct Access control is achieved by Control Register byte 1 bit 6.
19
17
DRAM A4:
DRAM address line A4.
20
18
DRAM A5:
DRAM address line A5.
21
19
DRAM A6:
DRAM address line A6.
22
20
DRAM A7:
DRAM address line A7.
23
21
DRAM A8:
DRAM address line A8.
24
Row Address Strobe 4 (RAS4): Should be connected to the Row Address Strobe input of the fourth 1Mbit DRAM chip (if fitted).
25
Row Address Strobe 3 (RAS3): Should be connected to the Row Address Strobe input of the third 1Mbit DRAM chip (if fitted).
26
22
DRAM A9: DRAM address line A9. This pin is not connected when a 256kbit DRAM is employed. Note: To simplify PCB layout, the DRAM address inputs A0 A8 may be connected in any physical order to the DVSR Codec output pins A0 A8.
27
23
Column Address Strobe (CAS): The DRAM Column Address Strobe pin. Should be connected to the CAS pins of all DRAM chips.
28
24
VDD: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the DVSR Codec are dependant upon this supply.
3
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