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Details, datasheet, quote on part number:FX803J
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| Part: | FX803J |
| Category: | Analog & Mixed-Signal Processing => Amplifiers => Audio/Power Amplifiers |
| Description: | Fx803 Audio Signalling Processor |
| Company: | Consumer Microcircuits Limited |
| Datasheet: | Download FX803J datasheet File size : 169 kB |
| Request For quote: | Find where to buy FX803J
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Datasheet text preview:
FX803 Audio Signalling Processor
SIGNAL INPUT BIAS DIGITAL NOISE (Rx) AUDIO IN INPUT AMPLIFIER VDD FILTER 1
Rx FILTER SWITCH
DIGITAL NOISE FILTER 2
QUALITY METER
PROGRAMABLE NOTONE TIMER
COMMAND DATA REPLY DATA C-BUS INTERFACE CHIP SELECT AND CONTROL LOGIC INTERRUPT SERIAL CLOCK LOGIC INPUT
GATE TIME GENERATOR
FREQUENCY COUNTER PROGRAMABLE (Tx PERIOD) TIMER
V BIAS
TONE 1 GENERATOR 5- / 2-TONE DTMF 1
LOW PASS FILTER
TONE 1 OUT
SUM IN SWITCHED SUM OUT V SS
SUMMING SWITCH CAL/CUES SWITCH
SUM OUT CAL/CUES OUT
V BIAS XTAL/CLOCK CLOCK GENERATOR XTAL AUDIO SWITCH IN
AUDIO SWITCH
CUES
SUMMING AMPLIFIER TONE 2 GENERATOR CUES / DTMF 2
CAL
LOW PASS FILTER
TONE 2 OUT
AUDIO SWITCH OUT
Fig.1 FX803 Audio Signalling Processor
FX803 Audio Signalling Processor
As part of the DBS 800 System, this audio signalling processor will provide an inband tone signalling facility for PMR radio systems. Signalling systems supported include Selcall (CCIR, ZVEI I, II and III, EEA), 2-Tone Selcall and Dual Tone Multi-Frequency (DTMF) encode. Using a non-predictive tone decoder and versatile encoders gives the FX803 the capability to work in any standard or non-standard tone system. This is a full-duplex device consisting of: q q q Two individual tone generators and a programmable (Tx) period timer. A tone decoder with programmable NOTONE Timer. An on-chip summing amplifier. Both tone generators can be individually placed into a power economical "Powersave" mode. A general purpose logic input, interfacing directly with the Status Register, is provided. This could be used as an auxiliary method of routeing digital information to the µController via the "C-BUS." The output frequencies are produced from data loaded to the device, with a programmable, general purpose, on-chip timer available to indicate the tone transmit periods. A Dual Tone Multi-Frequency (DTMF) output is obtained by combining the 2 independent output frequencies in the integral summing amplifier. This Summing Amplifier output is also available for level adjustment. Tones produced by the FX803 can also be used in the DBS 800 system as modulation calibration inputs and for "CUE" audio indications for the operator. Received tones are measured and their frequency indicated to the µController in the form of a received data word. A poor-quality or incoherent tone will, after a programmed period, indicate NOTONE. The FX803 is a low-power, 5-volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages.
For use with Single Tone or Selective Call systems. Under the control of the µController, via "C-BUS," the FX803 will encode and transmit a single or pair of audio tones, in the frequency range 208Hz to 3kHz, simultaneously, and detect, decode and indicate the frequency of non-predicted input tones in the frequency range 313Hz to 6kHz.
Publication D/803/6 April 1998
Pin Number Function
J/LG/LS
1
DW
1 Xtal: The output of the on-chip clock oscillator. External components are required at this input when a Xtal input is used. See Figure 2.
2
2
Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (fXTAL) should be connected here. See Figure 2.
3
3
Reply Data: The "C-BUS" serial data output to the µController. The transmission of Reply Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held at high-impedance when not sending data to the µController. See Timing Diagrams.
4
5
Chip Select (CS): The "C-BUS" data loading control function. This input is provided by the µController. Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagram.
5
6
Command Data: The "C-BUS" serial data input from the µController. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams.
6
7
Logic Input: This `real-time' input is available as a general purpose logic input port which can be read from the Status Register. See Table 3.
7
8
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by going to a logic "0." This is a "wire-or able" output, allowing the connection of up to 8 peripherals to 1 interrupt port on the µController. This pin has a low-impedance pulldown to logic "0" when active and a high-impedance when inactive. The System IRQ line requires one pullup resistor to VDD. The conditions that cause interrupts are indicated in the Status Register and are shown below: G/Purpose Timer Period Expired NOTONE Timer Period Expired Rx Tone Measurement Complete These interrupts are inactive during relevant Powersave conditions and can be disabled by Bits 5 and 6 in the Control Register.
8
4
No internal connection, connect to VSS.
9
9
No internal connection, connect to VSS.
10
10
Audio Switch In: The input to the stand-alone, on-chip Audio Switch. This switching function (Control Register Bit 7) may be used to break the system transmitter modulation path when it is required to provide a CUE (beep) from Tone Generator 2 to the loudspeaker via the FX806 PLMR Audio Processor.
11
11
Audio Switch Out: The output of the stand-alone, on-chip Audio Switch.
12
12
VSS: Negative Supply (Signal Ground).
2
Pin Number Function
J/LG/LS
13
DW
13 (Rx) Audio In: The received audio tone signalling input to the Input Amplifier. This input requires to be a.c. coupled and connected, using external components, to the Signal Input Bias pin. See Figure 2. Signal Input Bias: External components are required between this input and the (Rx) Audio In pin See Figure 2. VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C2 See Figure 2. Tone 1 Out: Tone 1 Generator (2-/5- tone Selcall or DTMF 1) output. External gain and coupling components will be required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to Tx Tone Generator 1 Register (Table 4). See Figure 2. Tone 2 Out: Tone 2 Generator (2-/5- tone Selcall, CUES or DTMF 2) output. External gain and coupling components will be required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to Tx Tone Generator 2 Register (Table 5). See Figure 2. CAL/CUES Out: An auxiliary, selectable tone frequency output, providing a square wave CALibration signal from Tone 2 Generator or a sine wave CUES (beep) signal from the Summing Amplifier. The output mode (CAL or CUES) is selected by Bit 14 in the Tx Tone Generator 2 Register (Table 5). In a DBS 800 audio installation, this output should be connected to the Calibration Input of the FX806 PLMR Audio Processor. When Tone Generator 2 is set to VBIAS (NOTONE), the CAL output is pulled to VBIAS and during a powersave of Tone Generator 2 it is held at VSS. Sum In: The input to the on-chip Summing Amplifier. This amplifier is available for combining Tone 1 and Tone 2 outputs (DTMF). Gain and coupling components should be used at this input to provide the required system gains. See Figures 2 and 3. Sum Out: The output of the on-chip Summing Amplifier. Combined tones (1 and 2) are available at this output. See Figures 2 and 3. Switched Sum Out: The combined tone output available for transmitter modulation. The switch allows control of the FX803 final output to the FX806. Control of this switch is by Bit 4 of the Control Register. See Figures 2 and 3. No internal connection, connect to VSS. Serial Clock: The "C-BUS" serial clock input. This clock, produced by the µController, is used for transfer timing of commands and data to and from the Audio Signalling Processor. See Timing Diagrams. VDD: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within the Audio Signalling Processor are dependent upon this supply. NOTE: (i) Further information on external components and DBS 800 system integration of this microcircuit are contained in the System Support Document.
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22 23
22 23
24
24
"C-BUS" is CML's proprietary standard for the transmission of commands and data between a µController and DBS 800 microcircuits. It may be used with any µController, and can, if desired, take advantage of the hardware serial I/O functions embodied into many types of µController. The "C-BUS" data rate is determined solely by the µController.
3
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