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Details, datasheet, quote on part number:FX805LG
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Datasheet text preview:
FX805 Sub-Audio Signalling Processor
Rx SUB-AUDIO OUT Rx LOWPASS Rx SUB-AUDIO IN COMPARATOR IN OUT
+
180Hz/260Hz COMPARATOR AMP Raw NRZ "Data"
DIGITAL NOISE FILTER
FREQUENCY ASSESMENT
NOTONE TIMER
NOTONE
OUT NRZ Rx DATA and BAUD RATE EXTRACTOR NRZ Rx Data Rx V BIAS Tx DATA BUFFER XTAL/CLOCK CLOCK GENERATOR XTAL NRZ Tx BAUD RATE CTCSS Tx TONE NRZ Rx CLOCK RATE Audio Signal Path AUDIO IN Audio By-Pass CTCSS "Sub-Audio" Frequency SUB-AUDIO BANDSTOP Tx LEVEL ADJUST and SHIFT REGISTER NRZ Tx Data Variable Bandwidth NRZ Rx Baud Rate FREQUENCY MEASUREMENT (COUNTER) C-BUS INTERFACE AND CONTROL LOGIC
COMMAND DATA REPLY DATA CHIP SELECT INTERRUPT SERIAL CLOCK WAKE ADDRESS SELECT
+
IN
Rx AMP VDD
Tx SUB-AUDIO OUT
V SS
Tx SUB-AUDIO LOWPASS AUDIO OUT
Fig.1 FX805 Sub-Audio Signalling Processor
FX805 Sub-Audio Signalling Processor
A µProcessor controlled, sub-audio frequency signalling processor to provide an outband audio and digital signalling facility for PMR radio systems. This device caters for the transmission and non-predictive reception of: q Continuous Tone Controlled Squelch (CTCSS) tones and other non-standard sub-audio frequencies. q Non-Return-to-Zero (NRZ) data to facilitate Continuous Digitally Coded Squelch (CDCS/DPLTM) system operations. To achieve these functions, the FX805 has on-chip: q A non-predictive CTCSS Tone Decoder and CDCS subaudio signal demodulator. q A CTCSS/NRZ Encoder with Tx level adjustment and lowpass filter output stage with optional NRZ pre-emphasis. q A selectable sub-audio bandstop filter. q A Notone (CTCSS Rx) period timer. Setting of the FX805 functions and modes is by data loaded from the µController to the controlling registers within the device. Reply Data and Interrupt protocol keep the µController up to date on the operational status of the circuitry all via the "C-BUS" interface. CTCSS tone data for transmission is generated within the µController, loaded to CTCSS Tx Frequency Register, encoded and output as a tone via the Tx Sub-Audio Lowpass Filter. TM Received non-predicted CTCSS tone frequencies are measured and the resulting data, in the form of a 2-byte data-word, is presented via the CTCSS Rx Frequency Register to the µController for matching against a `look-up' table. Noise filtering is provided to improve the signal quality prior to measurement. NRZ coded data streams for transmission, when generated within a µController, are loaded to the NRZ Tx Data Buffer and output, in 8-bit bytes, through the Lowpass Filter circuitry as sub-audio signals. CDCS turn-off tones can be added to the data signals by switching the FX805 to the CTCSS transmit mode at the appropriate time. NRZ coding is produced by the µController and translated into sub-audio signals by the FX805. Received NRZ data is filtered, detected and placed into the NRZ Rx Data Register which is then available for transfer one byte at a time, to the µController, for decoding by software. Clock extraction circuitry is provided on chip and Rx and Tx baud rates are selectable. Provision is made in both hardware and system software allocations to address two FX805 Sub-Audio Signalling Processors consecutively to achieve multi-mode, duplex operation. The FX805 has a powersaving function which may be controlled by software or a dedicated (Wake) input. The FX805 is a low-power, 5-volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages.
DPL is a registered trademark of Motorola Inc.
Publication D/805/3 July 1994
Pin Number Function
FX805 J/LG/LS
1 Xtal: The output of the on-chip clock oscillator. External components are required at this input when a Xtal (fXTAL) input is used. See Figure 2.
2
Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (fXTAL) should be connected here. See Figure 2.
3
Address Select: This pin enables two FX805 devices to be used on the same "C-BUS," providing fullduplex operation. See Tables 1 and 2.
4
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by going to a logic "0." This is a "wire-or able" output, allowing the connection of up to 8 peripherals to 1 interrupt port on the µController. This pin has a low impedance pulldown to logic "0" when active and a high impedance when inactive. The System IRQ line requires 1 pullup resistor to VDD. The conditions that cause interrupts are indicated in the Status Register (Table 4) and are shown below:
Rx CTCSS Tone Measurement Complete 1 NRZ Rx Data Byte Received NRZ Tx Buffer Ready
CTCSS NOTONE Timer Expired New NRZ Rx Data Received Before Last Byte Read NRZ Data Transmission Complete
5
Serial Clock: The "C-BUS" serial clock input. This clock, produced by the µController, is used for transfer timing of commands and data to and from the Sub-Audio Signalling Processor. See Timing Diagrams.
6
Command Data: The "C-BUS" serial data input from the µController. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams.
7
Chip Select (CS): The "C-BUS" data loading control function. This input is provided by the µController. Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagrams.
8
Reply Data: The "C-BUS" serial data output to the µController. The transmission of Reply Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held at high impedance when not sending data to the µController. See Timing Diagrams.
9
Tx Sub-Audio Out: The sub-audio output (pure or NRZ derived). Signals are band-limited, the Tx Output Filter has a variable bandwidth, see Table 6. This output is at VBIAS (a) when the NRZ Encoder is enabled but no data is being transmitted, (b) when the FX805 is placed in the Powersave All condition.
10
Audio In: The input to the switched sub-audio bandstop (highpass) filter. This input is internally biased and requires to be a.c. coupled by capacitor C7.
11
Audio Out: The output of the `audio signal path' (filter or by-pass). This output is controlled by the Control Register and when disabled is held at VDD/2.
12
VSS: Negative Supply (Signal Ground).
2
Pin Number Function
FX805 J/LG/LS
13 Rx Amp (-) In: The inverting input to the on-chip Rx Input Amp. See Figures 2, 3 and 4.
14
Rx Amp (+) In: The non-inverting input to the on-chip Rx Input Amp.
15
Rx Amp Out: The output of the on-chip Rx Input Op-Amp. This circuit may be used, with external components, as a signal amplifier and an anti-aliasing filter prior to the Rx Lowpass Filter, or for other purposes. See Figure 2 for component details.
16
Rx Sub-Audio In: The received sub-audio (CTCSS/NRZ) input. This input is internally biased to VDD/2 and requires to be a.c. coupled or biased. See Figure 2 for component details.
17
Rx Sub-Audio Out: The output of the Rx Lowpass Filter. This output may be coupled into the on-chip amplifier or comparator as required.
18
VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C8 (see Figure 2).
19
Comparator In (-): The inverting input to the on-chip "comparator" amplifier. See Figures 2, 3 and 4.
20
Comparator (+): The non-inverting input to the on-chip "comparator" amplifier. See Figures 2, 3 and 4.
21
Comparator Out: The output of the "comparator" amplifier. This node is also internally connected to the input of the Digital Noise Filter (see Figure 1). When both decoders are Powersaved, this output is at a logic "0."
22
NOTONE Timing: External RC components connected to this pin form the timing mechanism of a NOTONE period timer. The external network determines the `charge-rate' of the timer to VDD/2. Expiry of the timer will cause an interrupt. This facility is only used in the CTCSS Rx mode.
23
Wake: This `real-time ' input can be used to reactivate the FX805 from the `Powersave All' condition using an externally derived signal. The FX805 will be in a `Powersave All' condition when both this pin and Bit 0 of the Control Register are set to a logic "1." Recovery from "Powersave All" is achieved by putting either the Wake pin or the `Powersave All' bit to logic "0," thus allowing FX805 activation by the µController or an external signal, such as R.S.S.I. or Carrier Detect.
24
VDD: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within the SubAudio Signalling Processor are dependant upon this supply.
NOTE: (i) Further information on external components and DBS 800 system integration of this microcircuit are contained in the System Support Document. (ii) A glossary of abbreviations used in this document is supplied. (iii) Guidance upon the generation and manipulation of NRZ Rx and Tx data is given in DBS 800 Application Support Document.
"C-BUS" is CML's proprietry standard for the transmission of commands and data between a µController and DBS 800 microcircuits. It may be used with any µController, and can, if desired, take advantage of the hardware serial I/O functions embodied into many types of µController. The "C-BUS" data rate is determined soley by the µController.
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