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Details, datasheet, quote on part number:FX809LS
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Datasheet text preview:
FX809 FFSK Modem
Recovered Clock
CHECKSUM GEN/CHECK
VD D
BYTE COUNTER
Rx IN
FFSK RECEIVER
Recovered Clock
DATA REGISTER 1
DATA REGISTER 2
FFSK TRANSMITTER
TX OUT
XTAL/CLOCK CLOCK XTAL GENERATOR
Rx SYNC Detect
SYNC/SYNC DETECT
Rx SYNC Detect
VBIAS
Rx FREE FORMAT CS
RX DATA BUFFER
TX DATA BUFFER AMP IN
REPLY DATA
Rx Data Ready Interrupt Enable
Tx Data Ready
Tx Idle
SYNC PROGRAM LOW HIGH
+ AMP OUT
SERIAL CLOCK
C-BUS INTERFACE AND CONTROL LOGIC
8-Bit Parallel Bus
UNCOMMITTED VBIAS
Rx SYNC Detect Rx SYNC Detect
AMPLIFIER V SS
COMMAND DATA
ADDRESS DECODER
CONTROL REGISTER
STATUS REGISTER
INTERRUPT GENERATOR
IRQ
WAKE
ADDRESS SELECT
Fig 1. FX809 FFSK Modem
Brief Description
An intelligent, half-duplex, FFSK/MSK modem which operates under "C-BUS" control. In addition this modem provides software selectable checksum generation and error checking, in accordance with MPT1327. The FX809, using Interrupt and Status Register procedures, performs the functions described below: In Tx mode the FX809 will: 1. (a) Accept from the host and transmit, 8-bit bytes of data as instructed (Preamble, Sync, Address and data). (b) internally calculate and insert a 2 byte checksum based upon the preceeding 6 bytes of data, or (c) disable the internal checksum generator and continuously transmit the data supplied. 2. Transmit 1 hang-bit and go to Tx Idle when all loaded data bytes have been transmitted. In Rx mode the FX809 will: 1. Detect and achieve bit synchronization within 16 bits. 2. (a) Search and detect the user-programmed Sync (or its opposite logic sense) Word and achieve frame sychronization. Data will then be output in 8-bit bytes via the Rx Data Buffer. Publication D/809/5 April 1998 (b) Use the received checksum to calculate the presence of any errors, setting the Status Register accordingly. 3. Make the incoming data directly available, via the Rx Data Buffer (Rx Freeformat), overriding synchronization requirements. The FX809 achieves Rx input timing by recovering an Rx clock from the incoming data stream. Output tones are timed to the internally generated transmit clock. Filter, register clocks and transmit FFSK tone frequencies are derived internally from the external Xtal or clock pulse input. For compliance with the MPT 1327 Signalling Specification a 4.032MHz Xtal or clock input will be required.
NOTE: All information contained in this data sheet is specified using a 4.032 MHz Xtal, 1200 bps baud rate , Mark and Space frequencies 1200 Hz and 1800 Hz.
The FX809 is a low-power 5-volt integrated circuit, incorporating "Powersave" modes to further reduce power requirements. An uncommitted amplifier is provided on chip for general purpose applications within DBS 800. The FX809 is available in 24-pin cerdip DIL and 24pin/lead plastic SMD packages.
Pin Number Function
FX809 J/LG/LS 1 Xtal: The output of the on-chip clock oscillator. External components are required at this input when a Xtal input is used. See Figure 2, INSET.
2
Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock should be connected here. See Figure 2, INSET.
3
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the µController, by going to a logic "0." This is a "wire-or able" output, enabling the connection of up to 8 peripherals to 1 interrupt port on the µController. This pin has a low-impedance pulldown to logic "0" when active and a high-impedance when inactive. The system IRQ line requires a 'pull-up' resistor to VDD. The conditions that cause interrupts are indicated in the Status Register and are shown below: Tx Idle Rx Data Ready Tx Data Ready Rx SYNC Detect Rx SYNC Detect Interrupt outputs can be disabled by bit 3 of the Control Register.
No Internal connection. 4 No Internal connection. 5 Rx Freeformat: Used in the Rx mode, this input, when a logic "0," allows received data to be read from the Rx Data Buffer via the Reply Data line without having to acheive byte synchronization (SYNC/SYNC) first. Data will continue to be available after this input goes to a logic "1" until either a SYNC or SYNC Prime bit is set or the the modem set to Tx mode. When held at a logic "1" the modem operates normally. This pin has an internal 1M pullup resistor. NOTE: If this input is held at a logic "0" in the Tx mode, the Rx Data Ready bit in the Status Register may occasionally be set, but not cause an interrupt. If this input is a logic "0" when going into the Rx mode, an Rx Data Ready interrupt may be generated immediately, in this case the first byte of Rx data should be ignored.
6
7
VBIAS : The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C3, see Figure 2. Amp In: The inverting input to the on-chip uncommitted amplifier .
8 Amp Out: The output of the on-chip uncommitted amplifier. 9 Rx In: The 1200 baud, 1200Hz/1800Hz, received FFSK signal input. The input signal to this pin must be a.c. coupled via capacitor C4, see Figure 2. No Internal connection. 11 VSS: Negative Supply (GND).
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