Digchip : Database on electronics components
Electronics components database



Details, datasheet, quote on part number: MX919BDS
 
 
Part numberMX919BDS
CategoryCommunication => Modems => Analog Interface/Datapump
TitleAnalog Interface/Datapump
Description4-level FSK Modem Data Pump
CompanyConsumer Microcircuits Limited
DatasheetDownload MX919BDS datasheet
Request For QuoteFind where to buy MX919BDS
 


 
Specifications, Features, Applications

Features

· 4-Level Root Raised Cosine FSK Modulation Half Duplex, to 19.2kbps Increase Channel Bit Rate/Hz Full Data Packet Framing Impulse and NRZ Signal Modes Enhanced Performance in Noisy Conditions Error Detection and Error Correction Low Power 3.3V/5.0V Operation

Applications

· Wireless Data Terminals Two Way Paging Systems Digital Radio Systems Wide Area Wireless Data Broadcasts Point to Point Wireless Data Links

The is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host µC and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link. The MX919B assembles application data received from the host µC, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter. In receive mode, the MX919B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host µC. CRC detected residual uncorrected data errors will be flagged. A readout of the SNR value during receipt of a packet is also provided. The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies. The MX919B may be used with to 5.5V power supply and is available in the following package styles: 24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP (MX919BP).

All trademarks and service marks are held by their respective companies.

1. Block Diagram............................................................................................................... 6 2. Signal List...................................................................................................................... 7 3. External Components................................................................................................... 8 4. General Description...................................................................................................... 9

Data Bus Buffers..................................................................................................................... 9 Address and R/W Decode...................................................................................................... 9 Status and Data Quality Registers.......................................................................................... 9 Command, Mode, and Control Registers............................................................................... 9 Data Buffer.............................................................................................................................. 9 CRC Generator/Checker........................................................................................................ 9 FEC Generator/Checker......................................................................................................... 9 Interleave/De-Interleave Buffer............................................................................................... 9 Frame Sync Detect................................................................................................................. 9

4.1.10 Rx Input Amp........................................................................................................................ 10 4.1.11 RRC Low Pass Filter............................................................................................................ 4.1.12 Tx Output Buffer.................................................................................................................... 4.1.13 Rx Level/Clock Extraction..................................................................................................... 12 4.1.14 Clock Oscillator and Dividers................................................................................................ 12

Modem - µC Interaction................................................................................................... 12 Binary to Symbol Translation........................................................................................... 13 Frame Structure............................................................................................................... 14 The Programmer's View................................................................................................... 15

4.5.1 4.5.2 Data Block Buffer.................................................................................................................. 15 Command Register............................................................................................................... 15 Command Register B7: AQSC - Acquire Symbol Clock................................................ 16 Command Register B6: AQLEV - Acquire Receive Signal Levels................................. 16 Command Register B5: CRC........................................................................................ 16 Command Register B4: TXIMP - Tx Level/Impulse Shape............................................ 16 Command Register B3 - Reserved................................................................................ 16 Command Register B1, B0: TASK........................................................................... 16 NULL: No effect.............................................................................................................. 18 SFSH: Search for Frame Sync plus Header Block........................................................ 18 RHB: Read Header Block............................................................................................... 18

4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block....................................................................... 18 4.5.2.11 SFS: Search for Frame Sync......................................................................................... 4.5.2.12 R4S: Read 4 Symbols.................................................................................................... 4.5.2.13 T24S: Transmit 24 Symbols........................................................................................... 19 4.5.2.14 THB: Transmit Header Block.......................................................................................... 19 4.5.2.15 TIB: Transmit Intermediate Block................................................................................... 20 4.5.2.16 TLB: Transmit Last Block............................................................................................... 20

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

4.5.2.17 T4S: Transmit 4 Symbols............................................................................................... 20 4.5.2.18 RESET: Stop any current action.................................................................................... 20 4.5.2.19 Task Timing.................................................................................................................... 20 4.5.2.20 RRC Filter Delay............................................................................................................. 21 4.5.3 Control Register.................................................................................................................... 22 Control Register B7, B6: CKDIV - Clock Division Ratio................................................. 22 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches............. 22 Control Register B3, B2: LEVRES - Level Measurement Modes.................................. 23 Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes.................. 23 Mode Register B7: IRQEN - IRQ Output Enable......................................................... 24 Mode Register B6: INVSYM - Invert Symbols................................................................ 24 Mode Register B5: TX/RX - Tx/Rx Mode......................................................................

Mode Register B4: RXEYE - Show Rx Eye.................................................................... 25 Mode Register B3: PSAVE - Powersave........................................................................ 25 Mode Register B0.............................................................................................. 25 Status Register B7: IRQ - Interrupt Request.................................................................. 26 Status Register B6: BFREE - Data Block Buffer Free.................................................... 26 Status Register B5: IBEMPTY - Interleave Buffer Empty............................................... 26 Status Register B4: DIBOVF - De-Interleave Buffer Overflow....................................... 26 Status Register B3: CRCERR - CRC Checksum Error.................................................. 27 Status Register B0............................................................................................. 27

Data Quality Register............................................................................................................ 27 Cyclic Redundancy Codes.................................................................................................... CRC2.............................................................................................................................. 28 Forward Error Correction................................................................................................ 28 Interleaving..................................................................................................................... 28

Transmitted Symbol Shape.............................................................................................. 28 Transmit Frame Example................................................................................................. 30 Receive Frame Example.................................................................................................. 33 Clock Extraction and Level Measurement Systems.......................................................... 36

Supported Types of Systems................................................................................................ 36 Clock and Level Acquisition Procedures with RF Carrier Detect......................................... 36 Clock and Level Acquisition Procedure without RF Carrier Detect...................................... 36 Automatic Acquisition Functions........................................................................................... 37

AC Coupling..................................................................................................................... 37 Radio Performance.......................................................................................................... 39 Received Signal Quality Monitor...................................................................................... 40




Related products with the same datasheet
MX919BDW   MX919BLH   MX919BP  


Some Part number from the same manufacture Consumer Microcircuits Limited
MX919BDW 4-level FSK Modem Data Pump
MX929
MX929A
MX929B
MX929D5 Motient/ardis Rd-lap MDC4800 Modem
MX929E2
MX929P4
MX939
MX949
MX980
CMX7031 The CMX7031 or CMX7041 configured via FI-2.0 provides a half-duplex 4-level FSK modem suitable for use in PMR/LMR radios. In conjunction with a suitable host µcontroller and radio modules, this provides
CMX998 A Cartesian Loop improves the efficiency and linearity of transmitters for non-constant envelope modulation systems. The CMX998 is an integrated solution for a Cartesian Feedback Loop based linear transmitter. Acting
CMX910 Description Designed specifically for all current modes of AIS operation, the CMX910 offers a highly integrated IC capable of performing all of the required data-handling and formatting, timing, distribution
CMX865A The CMX865A is a multi-standard modem for use in Wireless Local Loop, Short Message Service telephone based information and telemetry systems. Flexible line driver, hybrid and receiver circuits are integrated
CMX7032 esigned for AIS Class B Implementation, the CMX7032 is a highly integrated, half-duplex, AIS baseband signalling processor IC with two on-chip RF synthesisers. Comprising two parallel limiter-discriminator
CMX7163 QAM Modem The CMX7163 QAM Modem is a low power half-duplex device supporting multiple channel spacings under host microcontroller (µC) control. Its Function Image™ (FI) is loaded to initialise the device
CMX994 RF Direct Conversion Receiver The CMX994 is a direct conversion receiver IC. The receiver is fully integrated with a broadband Low Noise Amplifier (LNA) preceding the down-converter section, a high dynamic-range
CMX7131 Digital PMR Processors Including DPMR And DCR Systems The CMX7131 and CMX7141 are half-duplex 4-Level FSK modem IC platforms built on FirmASIC™ technology and are suitable for use in digital radio systems,
CMX7261 The CMX7261 Multi-transcoder IC is a device supporting multiple speech codecs in a single chip. The CMX7261 is capable of encoding analogue voice into PCM (linear, ě-law or A-law), CVSD or G.729A data
CMX7045 The CMX7045 is a dedicated processor for marine Automatic Identification System (AIS), Search and Rescue Transmitter (SART) operation, fully meeting the requirements of IEC 61097-14. This highly integrated
CMX994 The CMX994 is a direct conversion receiver IC. The receiver is fully integrated with a broadband Low Noise Amplifier (LNA) preceding the down-converter section, a high dynamic-range I/Q demodulator. The