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Details, datasheet, quote on part number:PATHFINDER-1
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Catalina Research Product Datasheet
Pathfinder-1
High Performance Vector Processing Chip
Applications:
Radar/Sonar Signal Processing Signal Intelligence/Real Time Spectral Analysis Telecommunications Medical Electronics High Performance Instrumentation
Pathfinder-1 Benefits & Features
80 MHz Clock (Commercial Temperature Range 0°C to 70°C) 3.3V Operation Synchronous System Design 0.35 micron CMOS Three Layer Metal Process 24-and 32-Bit 2's Complement Block Floating Point (8-bit Exponent) Provides 192 dB Dynamic Range Distributed Internal Scaling Minimizes Round Off Errors Five Port Device Full Crossbar Multiplexing on all Ports Free Window or Filter Multiplications with the First Pass or an FFT of IFFT for All Radix Sizes Designed in VHDL Supported Opcodes Include Radix 2, 4, 16, 32 for Real and Complex Data Complex and Real Multiply Add, Subtract Single Channel Real FFTs Dual Channel Real FFTs Single Channel Real IFFTs Dual Channel Real IFFTs Magnitude Squared 500 Pin SBGA Package Compatible with CRI's Sojourner Address Generator
Catalina Research Product Datasheet
Pathfinder-1
Pathfinder-1 Benefits & Features
Pathfinder-1 is a high-performance digital signal processor optimized for computing general-purpose frequency-domain functions such as FFTs, IFFTs, real and complex multiplies, correlations, fast convolutions, and polyphase filters. Its high precision and handling of internal scaling enables Pathfinder-1 to process large vector sizes (up to 1 million complex samples) with dynamic range unmatched by any other commercially- available FFT processing integrated circuit. Pathfinder-1 provides a multi-port data flow structure designed to support concurrent I/O and processing, making the chip an excellent match for applications requiring very fast data throughput rates. Multiple Pathfinder-1 DSPs can be pipelined or cascaded for increased performance. The synchronous features of Pathfinder-1 combined with its five port I/O architecture allows straight forward system design. Performing a 1K complex FFT in 25.6 microseconds (80 MHz clock) makes Pathfinder-1 the fastest 32-bit, commerciallyavailable, FFT processor available today. Architectural Overview The Pathfinder-1 integrated circuit is built up from multiple complex multiplication stages, two radix-four cores, and one radix-two core. A unique feature of the Pathfinder-1 processing core is its distributed shift and round stages. This allows an improvement in dynamic range over more traditional block floating point architectures. Combined with its 32-bit precision, Pathfinder-1 offers the most dynamic range of any FFT processing chip currently available. Data Flow Pathfinder-1 provides five bidirectional I/O ports (please see the block diagram in Figure 1). The chip allows full cross-bar multiplexing on all five ports, enabling very flexible system designs and algorithm implementation. One benefit of the five port architecture is that cascaded processor designs become straight forward to implement. (Please see "Example System Architectures" for more details.) Another benefit of the port architecture is that no port needs to be designated exclusively as a coefficient port. Twiddle factors, windows, and filters may be stored in any memory bank connected to any of the five ports, and may be accessed at any time during processing. Additionally, the results from any processing pass may be broadcast simultaneously to up to two separate ports. This feature is fine for implementing algorithms where the intermediate results of a vector operation need to be stored and used later in the process, as it cuts down on the number of processing passes required. For example, previous FFT chip architectures required that results of a process pass flow into specific memories. Additional processing passes were necessary to move an intermediate result to other memory banks so it could be used later in the process. Since Pathfinder-1 has full cross-bar multiplexing on all five bi-directional ports, the need for extra move passes is eliminated thus increasing the performance of these types of algorithms. Tables 1 and 2 summarize the data flow function set for Pathfinder-1
Catalina Research Product Datasheet
Pathfinder-1
Pathfinder-1 System Architectures
DF Code Bit Positions Read Data Path Function Code (binary)
00000 00001 00010 00011 00100
DF(9:8) DF(9:8) DF(9:8) DF(9:8) DF(9:8)
C port select B2 port select B1 port select A2 port select A1 port select
Function
Throug hput latency (clks)
44 44 69 90 42
RADIX 2 RADIX 4 RADIX 16 RADIX 32 DUAL_CHANNEL_ REAL DUAL CHANNEL REAL INVERSE SINGLE_ CHANNEL_REAL SINGLE CHANNEL REAL INVERSE MAGNITUDE _SQUARED COMPLEX _MULTIPLY REAL_MULTIPLY ADD SUBTRACT FLOW RADIX_2R RADIX_4R RADIX_16R RADIX_32R
Table 1: Pathfinder-1 Port Selection
DF Code Bit Encoding Read Data Path
"00" "01" "10" "11"
data input twiddle input data output port is unused and is tri-state
00101
42
00110
42
Table 2: Pathfinder-1 Port Functionality
Example System Architectures
00111
42
Pathfinder-1 is designed to be used with pipelined sync-burst synchronous SRAM's and external address generators (such as CRI's Sojourner chip). The resulting design is a very flexible, high-performance frequency-domain processing engine that can be applied to a variety of demanding real-time DSP applications. An example system-level block diagram for a recursive architecture is provided in Figure 2. It supports concurrent I/O and processing, and provides a high degree of programmability. Figure 3 shows an example of a cascaded design. It is designed to maximize continuous throughput for a given algorithm Function Set Pathfinder-1's function set is optimized for frequency domain processing applications. It is a passbased processor where a given function opcode operates on an entire data vector. Table 3 summarizes Pathfinder-1's processing functions.
01000
41
01001 01010 01011 01100 01101 01110 01111 10000 10001
41 41 41 41 41 42 44 69 90
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