|Category||Memory => ROM => PROM|
|Company||Cypress Semiconductor Corp.|
|Datasheet||Download 5962-88735033X datasheet
Windowed for reprogrammability CMOS for optimum speed/power High speed 15-ns address set-up 10-ns clock to output Low power 330 mW (commercial) for 660 mW (military) Programmable synchronous or asynchronous output enable On-chip edge-triggered registers Programmable asynchronous register (INIT) EPROM technology, 100% programmable Slim, 300-mil, 24-pin plastic or hermetic DIP 5V ±10% VCC, commercial and military TTL-compatible I/O Direct replacement for bipolar PROMs Capable of withstanding greater than 2001V static discharge
The is a high-performance, x 8, electrically programmable, read only memory packaged in a slim 300-mil plastic or hermetic DIP. The ceramic package may be equipped with an erasure window; when exposed to UV light the PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C245A replaces bipolar devices and offers the advantages of lower power, reprogrammability, superior performance and high programming yield. The EPROM cell requires only 12.5V for the supervoltage, and low current requirements allow gang programming. The EPROM cells allow each memory location to be tested 100%, because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming the product will meet AC specification limits. The CY7C245A has an asynchronous initialize function (INIT). This function acts 2049th 8-bit word loaded into the on-chip register. It is user programmable with any desired word, or may be used as a PRESET or CLEAR function on the outputs. INIT is triggered by a low level, not an edge.
INIT A10 CP COLUMN ADDRESS DECODER PROGRAMMABLE INITIALIZE WORD ROW ADDRESS PROGRAMMABLE ARRAY MULTIPLEXER O5 8-BIT EDGETRIGGERED REGISTER O1 O0
Minimum Address Set-Up Time Maximum Clock to Output Maximum Operating Standard Current 7C245A-25 7C245A-35 Unit ns mA
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage to +150°C Ambient Temperature with Power to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin +7.0V DC Voltage Applied to Outputs in High +7.0V DC Input +7.0V DC Program Voltage (Pins 13.0V UV Erasure................................................... 7258 Wsec/cm2 Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mADescription
Output HIGH Voltage VCC = Min., IOH -4.0 mA VIN = VIH or VIL Output LOW Voltage Input HIGH Level Input LOW Level VCC = Min., IOL 16 mA VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for All Inputs Guaranteed Input Logical LOW Voltage for All Inputs
Input Leakage Current GND < VIN < VCC Input Clamp Diode Voltage Output Leakage Current Output Short Circuit Current GND VO < VCC Output Disabled VCC = Max., VOUT = 0.0V Com'l Mil
Power Supply Current VCC = Max., IOUT 0 mA Programming Supply Voltage Programming Supply Current Input HIGH Programming Voltage Input LOW Programming Voltage
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions = 1 MHz, VCC = 5.0V Max. 10 Unit pF
Notes: 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing. 5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 250 3.0V GND 5 ns ALL INPUT PULSES ns
7C245A-15 Parameter tSA tHA tCO tPWC tSES tHES tDI tRI tPWI tCOS tHZC tDOE tHZE Description Address Set-Up to Clock HIGH Address Hold from Clock HIGH Clock HIGH to Valid Output Clock Pulse Width ES Set-Up to Clock HIGH ES Hold from Clock HIGH Delay from INIT to Valid Output INIT Recovery to Clock HIGH INIT Pulse Width Valid Output from Clock HIGH Inactive Output from Clock HIGH Valid Output from E LOW Inactive Output from E HIGH Min. 7C245A-18 Max. 7C245A-35 Min. Max. 7C245A-25 Min. Max. 7C245A-35 Min. 0 25 Max. Unit ns Max. Min.
Notes: 7. Applies only when the synchronous (ES) function is used. 8. Applies only when the asynchronous (E) function is used.
The is a CMOS electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin replacement for bipolar TTL fusible link PROMs. The CY7C245A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM data is stored temporarily in a register. Additional flexibility is provided with a programmable synchronous (ES) or asynchronous (E) output enable and asynchronous initialization (INIT). Upon power-up the state of the outputs will depend on the programmed state of the enable function (ES or E). If the synchronous enable (ES) has been programmed, the register will be in the set condition causing the outputs be in the OFF or high-impedance state. If the asynchronous enable (E) is being used, the outputs will come up in the OFF or high-impedance state only if the enable (E) input at a HIGH logic level. Data is read by applying the memory location to the address inputs (A0A10) and a logic LOW Document 38-04007 Rev. *B
to the enable input. The stored data is accessed and loaded into the master flip-flops of the data register during the address set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (O0O7). If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic LOW. If the synchronous enable (ES) is being used, the outputs will go to the OFF or high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the output to the active state. Following a positive clock edge, the address and synchronous enable inputs are free to change since no change in the output will occur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C245A decoders and sense amplifiers to access the next location while previously addressed data remains stable on the outputs.
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