Details, datasheet, quote on part number: 5962-8946801XC
Part5962-8946801XC
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => EPLD (Erasable PLD)
TitleEPLD (Erasable PLD)
DescriptionMAX340 High-density Epld
CompanyCypress Semiconductor Corp.
DatasheetDownload 5962-8946801XC datasheet
Quote
Find where to buy
 
  

 

Features, Applications

Features

192 macrocells in 12 logic array blocks (LABs) Eight dedicated inputs, 64 bidirectional I/O pins 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages

The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.

The is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions. The 192 macrocells in the CY7C341 are divided into 12 LABs, 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341 allows them to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341 allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341 reduces board space and part count, and increases system reliability. Each LAB contains 16 macrocells. In LABs F, G, and L, eight macrocells are connected to I/O pins and eight are buried, while for LABs I, J, and K, four macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell.

Timing delays within the CY7C341 may be easily determined using WarpTM, Warp ProfessionalTM, or Warp EnterpriseTM software. The CY7C341 has fixed internal delays, allowing the user to determine the worst case timing delays for any design.

For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.

The CY7C341 contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device. The CY7C341 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.

There are 12 logic array blocks in the CY7C341. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C341 provides eight dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow.

Commercial Industrial Military Commercial Industrial Military

SYSTEMCLOCK (A1) (B2) LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9­16 LAB (C1) (D2) MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21­32 LAB G MACROCELL 97 MACROCELL 98 MACROCELL 99 MACROCELL 100 MACROCELL 101 MACROCELL 102 MACROCELL 103 MACROCELL 104 MACROCELL 105­112 LAB H MACROCELL 113 MACROCELL 114 MACROCELL 115 MACROCELL 116 MACROCELL (J11) (H10)

LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELL 89­96

LAB L MACROCELL 177 MACROCELL 178 MACROCELL 179 MACROCELL 180 MACROCELL 181 MACROCELL 182 MACROCELL 183 MACROCELL 184 MACROCELL 185­192 VCC GND




EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
REGISTER tCLR tPRE tRSU tRH tRD tCOMB tLATCH OUTPUT DELAY tOD tXZ tZX INPUT/ OUTPUT
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC LOGIC ARRAY DELAY tFD I/O DELAY tIO

 

Related products with the same datasheet
5962-8946805XC
5962-8946805YA
5962-9061102XX
5962-9061102YX
5962-9206202MYX
5962-9314401MUX
5962-9314402MUX
5962-9314402MZX
CY7C341-25HC
CY7C341-25JC
CY7C341-30JC
Some Part number from the same manufacture Cypress Semiconductor Corp.
5962-8946801YA MAX340 High-density Epld
5962-8946805XC
5962-8981701ZX
5962-89839132X Electrically Erasable Industry Standard SPLD
5962-8984102LX
5962-90555023X
5962-9061102XX MAX340 High-density Epld
5962-9314401MZX
5962-9314402MUX
5962-95600 512k X 8 Static RAM
5962-9759701QXA FLASH370i CPLD
5962-9952101QYA Ultra37000 CPLD
ADSLUSBMODEM High-performance External Usb Modem
AN2121S Microcontroller
AN2135SC Ez-usb Full-speed Peripheral
AN2136S Microcontroller
AN2136SC Ez-usb Full-speed Peripheral
AN2720SC Anchor Chips Single-chip Ez-link
AN2720SC-01 Ez-usb Full-speed Peripheral
AN3042QC Co-mem Lite(tm) Pci Controller
B9940L
Same catergory

82C237 : FPGA/PLD Soft Core. CMOS High Performance Programmable Dma Controller.

ATF1504AE : Second Generation Industry Compatible 3.3V Logic Doubling CPLDS 64 Macrocells, Standard Power W/isp.

ATF1508A : EE Programmable CPLD. High-performance Eepld. Programmable Logic Device ­ 128 Macrocells ­ 5 Product Terms per Macrocell, Expandable to 40 per Macrocell Pins 7.5 ns Maximum Pin-to-pin Delay ­ Registered Operation to 125 MHz ­ Enhanced Routing Resources Flexible Logic Macrocell ­ D/T/Latch Configured Flip-flops ­ Global and Individual Register Control Signals ­ Global and Individual Output Enable.

ATF750C : EE Programmable CPLD. High-speed Complex Programmable Logic Device. Advanced, High-speed, Electrically-erasable Programmable Logic Device ­ Superset 22V10 ­ Enhanced Logic Flexibility ­ Backward Compatible with ATV750B/BL and ATV750/L Low-power Edge-sensing "L" Option with 1 mA Standby Current D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 7.5 ns Maximum Pin-to-pin Delay with 5V Operation Highest Density.

CoolRunner-II : Coolrunner-ii CPLD Family. Optimized for 1.8V systems - Industry's fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from to 512 macrocells Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation to 3.3V Advanced system - Fastest in system programming 1.8V ISP using IEEE 1532.

CY7C346B : UV SPLD. 128-Macrocell Max Epld. 128 macrocells in eight logic array blocks (LABs) 20 dedicated inputs, to 64 bidirectional I/O pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346B are divided into eight LABs, 16 per LAB. There are 256 expander product.

FLEX8000Family : SRAM-based FPGA/PAL. Programmable Logic Device Family. Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table to 16,000 usable gates to 1,500 registers System-level ­ In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller ­ Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus , Revision.

GAL20RA10B : GAL20RA10B (5.0V)10 Macrocells. High-Speed Asynchronous E2CMOS PLD Generic Array LogicTM HIGH PERFORMANCE E2CMOS ® TECHNOLOGY 7.5 ns Maximum Propagation Delay Fmax = 83.3 MHz 9 ns Maximum from Clock Input to Data Output TTL Compatible 8 mA Outputs UltraMOS® Advanced CMOS Technology to 75% REDUCTION IN POWER FROM BIPOLAR 75mA Typical Icc ACTIVE PULL-UPS ON ALL PINS E CELL TECHNOLOGY.

iSPLSI2192VE-100LB144 : 3.3v In-system Programmable Superfast High Density PLD. 3.3V In-System Programmable SuperFASTTM High Density PLD SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 8000 PLD Gates 96 I/O Pins, Nine or Twelve Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Pinout Compatible with.

iSPLSI5512VA-100LB388 : In-system Programmable 3.3v Superwide High Density PLD. In-System Programmable 3.3V SuperWIDETM High Density PLD SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 24000 PLD Gates / 512 Macrocells to 288 I/O Pins 512 Registers High-Speed Global Interconnect SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance SuperWIDE Input Gating (68 Inputs).

JBP28L42 : PROMs.

PA7540 : Fuse-based FPGA/PAL. Pin-compatible Superset of 26v12, 24v10, And 26v12.

PEEL22CV10AZ : 12 Inputs 10 I/os 10 Registers 12 Configurable Macro Cells 24/28 Pins 5V Zero Power SPLD.

QL3006 : Pasic High-Speed, Low Power, Instant-On, High Security Fpgas. 400 MHz Datapaths 0.35 µm four-layer metal non-volatile CMOS process for smallest die sizes to the logic cell flip-flop clock, set and reset inputs each driven by an input-only pin Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output.

TIBPAL16R6-20M : PALs. High-performance Impact (tm) Pal(r) Circuits. TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M HIGH-PERFORMANCE IMPACT TM PAL® CIRCUITS High-Performance Operation: Propagation Delay C Suffix. 15 ns Max M Suffix. 20 ns Max Functionally Equivalent, but Faster Than PAL16R4A, PAL16R6A, and PAL16R8A Power-Up Clear on Registered.

TIBPAL16R6-25C : PALs. Low-power High-performance Impact (tm) Pal(r) Circuits. High-Performance Operation: Propagation Delay C Suffix. 25 ns Max M Suffix. 30 ns Max Functionally Equivalent, but Faster Than PAL16R4A, PAL16R6A, and PAL16R8A Power-Up Clear on Registered Devices (All Register Outputs Are Set High, but Voltage Levels at the Output Pins Go Low) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition.

TIBPAL16R8-25CFN : PALs. ti TIBPAL16R8-25C, Low-power High-performance Impact<TM> PAL<R> Circuits.

TIBPAL20R6-5 : Fuse-based FPGA/PAL. High Performance Impact-x Pal Circuit. High-Performance Operation: fmax (no feedback) TIBPAL20R' -5C Series. 125 MHz Min TIBPAL20R' -7M Series. 100 MHz Min fmax (internal feedback) TIBPAL20R' -5C Series. 125 MHz Min TIBPAL20R' -7M Series. 100 MHz Min fmax (external feedback) TIBPAL20R' -5C Series. 117 MHz Min TIBPAL20R' -7M Series. 74 MHz Min Propagation Delay TIBPAL20L8-5C Series. 5 ns Max TIBPAL20L8-7M.

LFE2M20SE-5F484I : LatticeECP2/M Family Data Sheet The LatticeECP2/M family of FPGA devices is optimized to deliver high performance such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm.

 
0-C     D-L     M-R     S-Z