|Category||FPGAs/PLDs => PLDs (Programmable Logic Devices) => EPLD (Erasable PLD)|
|Title||EPLD (Erasable PLD)|
|Description||MAX340 High-density Epld|
|Company||Cypress Semiconductor Corp.|
|Datasheet||Download 5962-8946801YA datasheet
|Cross ref.||Similar parts: idt1235|
128 macrocells in eight logic array blocks (LABs) Eight dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array Advanced 0.65-micron CMOS technology to increase performance Available in 68-pin HLCC, PLCC, and PGA packages The 128 macrocells in the CY7C342B are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C342B allows to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342B reduces board space, part count, and increases system reliability.
The is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX® architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions.
SYSTEM CLOCK LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 916 LAB B MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL I A LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121128 LAB G MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 MACROCELL (C10) 58LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36 MACROCELL 37 MACROCELL 3848
LAB F MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 8696
LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52 MACROCELL 53 MACROCELL 54 MACROCELL 55 MACROCELL 56 MACROCELL G10, B7) VCC GND
LAB E MACROCELL 72 MACROCELL 71 MACROCELL 70 MACROCELL 69 MACROCELL 68 MACROCELL 67 MACROCELL 66 MACROCELL 65 MACROCELL 7380
There are eight logic array blocks in the CY7C342B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C342B provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O pins that may be individually configured for input, output, or bidirectional data flow. placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Timing delays within the CY7C342B may be easily determined using Warp®, Warp ProfessionalTM, or Warp EnterpriseTM software by the model shown in Figure 1. The CY7C342B has fixed internal delays, allowing the user to determine the worst-case timing delays for any design.
Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C342B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have.
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals that may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without the multiple internal logicREGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
SYSTEM CLOCK DELAY tICS CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO
Figure 1. CY7C342B Internal Timing Model Document 38-03014 Rev. *A Page of 14
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