Details, datasheet, quote on part number: 5962-89839132X
Part5962-89839132X
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => SPLDs (Simple PLD)
DescriptionElectrically Erasable Industry Standard SPLD
CompanyCypress Semiconductor Corp.
DatasheetDownload 5962-89839132X datasheet
Cross ref.Similar parts: 5962-85155 012X, 5962-85155 022X, 5962-85155 032X, 5962-85155 042X, 5962-85155 052X, 5962-85155 062X, 5962-85155 072X, 5962-85155 082X, 5962-88515 012X, 5962-88515 022X
Quote
Find where to buy
 
  

 

Features, Applications

Flash Erasable, Reprogrammable CMOS PAL® Device
Features

Active pull-up on data input pins Low power version 55 mA max. commercial 15, 25 ns) 65 mA max. industrial 15, 25 ns) 65 mA military (15 and 25 ns) Standard version has low power 90 mA max. commercial 15, 25 ns) 115 mA max. commercial (7 ns) 130 mA max. military/industrial 15, 25 ns) CMOS Flash technology for electrical erasability and reprogrammability PCI compliant User-programmable macrocell Output polarity control Individually selectable for registered or combinatorial operation to 16 input terms and 8 outputs 7.5 ns com'l version 5 ns tCO 7.5 ns tPD 125-MHz state machine 10 ns military/industrial versions 7 ns tCO 10 ns tPD 62-MHz state machine High reliability Proven Flash technology 100% programming and functional testing

The Cypress is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell.


The PALCE16V8 is executed 20-pin 300-mil molded DIP, a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. The device provides to 16 inputs and 8 outputs. The PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 20-pin PLDs such 16R8, 16R6, and 16R4. The PALCE16V8 features 8 product terms per output and 32 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control as a data product term. There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself.

Power-Up Reset All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. Electronic Signature An electronic signature word is provided in the PALCE16V8 that consists of 64 bits of programmable memory that can contain user-defined data. Security Bit A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE16V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled.

CG1 CL0x Cell Configuration Registered Output Combinatorial I/O Combinatorial Output Input Combinatorial I/O Devices Emulated Registered Med PALs Registered Med PALs Small PALs Small PALs 16L8 only


 

Related products with the same datasheet
5962-8983913RX
PALCE16V8-10JC
PALCE16V8-10JCT
PALCE16V8-10PC
PALCE16V8-15JC
PALCE16V8-15PC
PALCE16V8-25JC
PALCE16V8-25PC
PALCE16V8-7JC
PALCE16V8-7PC
Some Part number from the same manufacture Cypress Semiconductor Corp.
5962-8983913RX Electrically Erasable Industry Standard SPLD
5962-8984102LX
5962-90555023X
5962-9061102XX MAX340 High-density Epld
5962-9314401MZX
5962-9314402MUX
5962-95600 512k X 8 Static RAM
5962-9759701QXA FLASH370i CPLD
5962-9952101QYA Ultra37000 CPLD
ADSLUSBMODEM High-performance External Usb Modem
AN2121S Microcontroller
AN2135SC Ez-usb Full-speed Peripheral
AN2136S Microcontroller
AN2136SC Ez-usb Full-speed Peripheral
AN2720SC Anchor Chips Single-chip Ez-link
AN2720SC-01 Ez-usb Full-speed Peripheral
AN3042QC Co-mem Lite(tm) Pci Controller
B9940L
B9946
B9947
B9948
Same catergory

5962-85155102A : PALs. ti TIBPAL16R8-15M, High-performance Impact<TM> PAL<R> Circuits.

5962-85155212A : PALs. ti TIBPAL16R8-7M, High-performance Impact-X<TM> PAL<R> Circuits.

5962-87671193A : PALs. ti TIBPAL20R8-7M, High-performance Impact-X<TM> PAL<R> Circuits.

5962-9952101QYA : Ultra37000 CPLD. In-System ReprogrammableTM (ISRTM) CMOS CPLDs JTAG interface for reconfigurability Design changes do not cause pinout changes Design changes do not cause timing changes High density to 512 macrocells to 264 I/O pins Five dedicated inputs including four clock pins Simple timing model No fanout delays No expander delays No dedicated vs. I/O pin delays.

ATF1502AE : Second Generation Industry Compatible 3.3V Logic Doubling CPLDS 32-512 Macrocells, Standard Power W/isp.

ATF2500C : EE Programmable SPLD. High-speed Programmable Logic Device. High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells ­ 48 Flip-flops ­ Two per Macrocell ­ 72 Sum Terms ­ All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Product Term or Direct.

CC318F : FPGA/PLD Soft Core. Ppp8 HDLC Core. 4046 Clipper Court Fremont, CA 94538 USA. Phone: +1 510-770-2277 Fax: +1 510-770-2288 Email: sales@coreel.com URL: www.coreel.com Supports 4000X, VirtexTM, VirtexTM-E, and SpartanTM-II devices Conforms to RFC1619 PPP Over SONET Supports programmable Address, Control and Protocol fields Supports 8-bit Packet interface and PHY Framer interface Allows.

CW901101 : FPGA/PLD Soft Core. 10-bit Pipelined ADC Core. CW901101 10-Bit Pipelined ADC Core Overview The CW901101 is a high-performance 10-bit 45MSPS analog-to-digital converter (ADC) core targeted for digital receivers of cable modems, digital set-top boxes or digital TVs (DTV). The core is compatible with LSI Logic's FlexStream® ASIC design environment to enable seamless integration of the mixed-signal.

EPM7064S : EE Programmable SPLD. Max 7000 Programmable Logic Device Family (1250 Gates).

GAL26CLV12 : Low Voltage E2cmos PLD Generic Array Logic. HIGH PERFORMANCE E2CMOS® TECHNOLOGY 5 ns Maximum Propagation Delay Fmax = 200 MHz 3.5 ns Maximum from Clock Input to Data Output UltraMOS® Advanced CMOS Technology 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE JEDEC-Compatible 3.3V Interface Standard Inputs and I/O Interface with Standard 5V TTL Devices ACTIVE PULL-UPS ON ALL PINS E2 CELL TECHNOLOGY Reconfigurable.

GAL26CLV12D : GAL Family. GAL26CLV12D (3.3V)12 Macrocells. HIGH PERFORMANCE E2CMOS® TECHNOLOGY 5 ns Maximum Propagation Delay Fmax = 200 MHz 3.5 ns Maximum from Clock Input to Data Output UltraMOS® Advanced CMOS Technology 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE JEDEC-Compatible 3.3V Interface Standard Inputs and I/O Interface with Standard 5V TTL Devices ACTIVE PULL-UPS ON ALL PINS E2 CELL TECHNOLOGY Reconfigurable.

ispLSI2032VE : Isplsi 2032VE (3.3V)32 Macrocells. 3.3V In-System Programmable High Density SuperFASTTM PLD SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional, JEDEC and Pinout.

ispLSI2096E : Isplsi 2096E (5.0V)96 Macrocells. In-System Programmable SuperFASTTM High Density PLD SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional/JEDEC Upward Compatible.

iSPLSI3256A-50LM : In-system Programmable High Density PLD. HIGH-DENSITY PROGRAMMABLE LOGIC 128 I/O Pins 11000 PLD Gates 384 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic HIGH-PERFORMANCE E CMOS TECHNOLOGY fmax = 90 MHz Maximum Operating Frequency tpd 12 ns Propagation Delay TTL Compatible Inputs and Outputs.

JBP28L22MJ : PROMs. ti JBP28L22, 256x8 Bi-polar Prom.

PEEL16CV8 : 10 Inputs 8 I/os 8 Registers 4 Configurable Macro Cells 20 Pins 5V SPLD.

TIBPAL16R4-7CFN : PALs. ti TIBPAL16R4-7C, High-performance Impact-X<TM> PAL<R> Circuits.

TIBPAL22VP10-20CFN : PALs. ti TIBPAL22VP10-20C, High-performance Impact-X<TM> Programmable Array Logic Circuits.

TIMERCOUNTERTC : FPGA/PLD Soft Core. 32-bit Embedded Core Peripheral. Compatible with an Embedded ARM7TDMITM Processor Three 16-bit Timer/Counter Channels A Wide Range of Functions Including: ­ Frequency Measurement ­ Event Counting ­ Interval Measurement ­ Pulse Generation ­ Delay Timing ­ Pulse Width Modulation Each Timer/Counter Channel has 3 External Clock Inputs, 5 Internal Clock Inputs, and 2 Multi-purpose Input/Output.

 
0-C     D-L     M-R     S-Z