Details, datasheet, quote on part number: 5962-90555023X
Part5962-90555023X
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => SPLDs (Simple PLD)
DescriptionElectrically Erasable Industry Standard SPLD
CompanyCypress Semiconductor Corp.
DatasheetDownload 5962-90555023X datasheet
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Features, Applications

Features

Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability to 20 input terms 10 programmable I/O macrocells Output macrocell programmable as combinatorial or asynchronous D-type registered output Product-term control of register clock, reset and set and output enable Register preload and power-up reset Four data product terms per output macrocell Fast Commercial tPD 15 ns tCO 15 ns tSU 7 ns

ICC max 85 mA (Military) High reliability Proven EPROM technology >2001V input protection 100% programming and functional testing Windowed DIP, windowed LCC, DIP, LCC, PLCC available

The Cypress is a high-performance, second-generation programmable logic device employing a flexible macrocell structure that allows any individual output to be configured independently as a combinatorial output as a fully asynchronous D-type registered output. The Cypress PLDC20RA10 provides lower-power operation with superior speed performance than functionally equivalent bipolar devices through the use of high-performance 0.8-micron CMOS manufacturing technology. The PLDC20RA10 is packaged a 24 pin 300-mil molded DIP, a 300-mil windowed cerDIP, and a 28-lead square leadless chip carrier, providing to 20 inputs and 10 outputs. When the windowed device is exposed to UV light, the 20RA10 is erased and can then be reprogrammed.


Generic Part Number 20RA10-25 20RA10-35 tPD ns Com`l 15 20 Mil 25 35 Com'l 7 10 tSU ns Mil 15 20 Com'l 15 20 tCO ns Mil 25 35 Com'l 80 tCC ns Mil 85

Figure 1 illustrates the architecture of the 20RA10 macrocell. The cell dedicates three product terms for fully asynchronous control of the register set, reset, and clock functions, as well as, one term for control of the output enable function. The output enable product term output is ANDed with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from both sources. If product-term-only control is selected, it is automatically chosen for all outputs since, for this case, the external output enable pin must be tied LOW. The active polarity of each output may be programmed independently for each output cell and is subsequently fixed. Figure 2 illustrates the output enable options available. When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term outputs to be HIGH under all input conditions. This is achieved by programming all input term programming cells for these two product terms. Figure 3 illustrates the available output configuration options. An additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-defined logic functions.

Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a total of nine programmable plus ten dedicated inputs (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable I/O cells configured as outputs. Each input pin available in a given configuration is available as an input to the four control

Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the "no connect" (NC) pins

product terms and four uncommitted product terms of each programmable I/O macrocell that has been configured as an output. An I/O cell is programmed as an input by tying the output enable pin (pin 13) HIGH or by programming the output enable product term to provide a LOW, thereby disabling the output buffer, for all possible input combinations. When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation.

Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each register to be set by loading each register from an external source prior to exercising the device. Testing of complex state machine designs is simplified by the ability to load an arbitrary state without cycling through long test vector sequences to reach the desired state. Recovery from illegal states can be verified by loading illegal states and observing recovery. Preload of a particular register is accomplished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin to a logic LOW level. If the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. To insure predictable system initialization, all registers are preset to a logic LOW state upon power-up, thereby setting the active LOW outputs to a logic HIGH.

Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10

 

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