|Category||FPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD)|
|Company||Cypress Semiconductor Corp.|
|Datasheet||Download 5962-9759701QXA datasheet
|Cross ref.||Similar parts: CY7C372I-66YM|
128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology JTAG Interface Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed fMAX = 125 MHz tPD 5.5 ns tCO = 6.5 ns Fully PCI compliant or 5.0V I/O operation Available in 160-pin TQFP, CQFP, and PGA packages
The is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C375i is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C375i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.
7C375i100 7C375i83 Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output , tCO (ns) Typical Supply Current, ICC (mA)
Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V
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