Details, datasheet, quote on part number: 5962-9759701QXA
Part5962-9759701QXA
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD)
DescriptionFLASH370i CPLD
CompanyCypress Semiconductor Corp.
DatasheetDownload 5962-9759701QXA datasheet
Cross ref.Similar parts: CY7C372I-66YM
Quote
Find where to buy
 
  

 

Features, Applications

Features

128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable (ISRTM) Flash technology JTAG Interface Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed fMAX = 125 MHz tPD 5.5 ns tCO = 6.5 ns Fully PCI compliant or 5.0V I/O operation Available in 160-pin TQFP, CQFP, and PGA packages

The is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C375i is designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C375i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.

7C375i­100 7C375i­83 Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) Maximum Clock to Output , tCO (ns) Typical Supply Current, ICC (mA)

Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V



 

Related products with the same datasheet
5962-9759801QYA
5962-9759802QYA
5962-9759901QZC
5962-9759902QXC
5962-9759902QZC
CY7C375I-125AC
CY7C375I-66AC
Some Part number from the same manufacture Cypress Semiconductor Corp.
5962-9759801QYA FLASH370i CPLD
5962-9952101QYA Ultra37000 CPLD
ADSLUSBMODEM High-performance External Usb Modem
AN2121S Microcontroller
AN2135SC Ez-usb Full-speed Peripheral
AN2136S Microcontroller
AN2136SC Ez-usb Full-speed Peripheral
AN2720SC Anchor Chips Single-chip Ez-link
AN2720SC-01 Ez-usb Full-speed Peripheral
AN3042QC Co-mem Lite(tm) Pci Controller
B9940L
B9946
B9947
B9948
B9948L
B9949
C9950
CG6233AS Mpeg Clock Generator With Vcxo
CG6234AS
CG6235AS
CPLDFamilyFLASH370 Ultralogic 32-macrocell Flash CPLD
Same catergory

5962-85155162A : PALs. ti TIBPAL16R4-12M, High-performance Impact-X<TM> PAL<R> Circuits.

5962-89839132X : Electrically Erasable Industry Standard SPLD. Flash Erasable, Reprogrammable CMOS PAL® Device Active pull-up on data input pins Low power version 55 mA max. commercial 15, 25 ns) 65 mA max. industrial 15, 25 ns) 65 mA military (15 and 25 ns) Standard version has low power 90 mA max. commercial 15, 25 ns) 115 mA max. commercial (7 ns) 130 mA max. military/industrial 15, 25 ns) CMOS Flash technology.

82C37A : FPGA/PLD Soft Core. CMOS High Performance Programmable Dma Controller.

ATF1516A : EE Programmable CPLD. High-performance Ee-cpld. to 3.6V Operating Range with 5V Tolerant I/Os Macrocells with Enhanced ­ Pin-compatible with Industry-standard Devices ­ Speeds 4.5 ns Maximum Pin-to-pin Delay ­ Registered Operation to 225 MHz Enhanced Macrocells with Logic DoublingTM ­ Bury Either Register or COM while Using the Other for Output ­ Dual Independent Feedback Allows Multiple Latch Functions.

CW901101 : FPGA/PLD Soft Core. 10-bit Pipelined ADC Core. CW901101 10-Bit Pipelined ADC Core Overview The CW901101 is a high-performance 10-bit 45MSPS analog-to-digital converter (ADC) core targeted for digital receivers of cable modems, digital set-top boxes or digital TVs (DTV). The core is compatible with LSI Logic's FlexStream® ASIC design environment to enable seamless integration of the mixed-signal.

FLIP8051PR : FPGA/PLD Soft Core. Core. Core Specifics See Table 1 Provided with Core Documentation Manual; User Guide Design File Formats EDIF netlist, NCD netlist, VHDL source available extra Constraints File xflip52.ucf Verification Test vectors, VHDL testbench available extra Instantiation VHDL, Verilog Templates Reference designs & User Guide application notes Additional Items Bus Monitor.

ispLSI5128VE-100LT128 : Isplsi 5128VE (3.3V)128 Macrocells. In-System Programmable 3.3V SuperWIDETM High Density PLD Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE 3.3V Power Supply User Selectable 3.3V/2.5V I/O 6000 PLD Gates / 128 Macrocells 96 I/O Pins Available 128 Registers High-Speed Global Interconnect SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance.

PA7140 : EE Programmable SPLD. Pin-compatible Superset of Ep910, More Logic Than Epm7032/ Mach110.

PEEL22LV10AZ : EE Programmable CPLD. Pin-compatible Superset of 16v8/22v10, Zero Power 3v Schmitt Trigger.

PEEL22LV10AZ : 12 Inputs 10 I/os 10 Registers 12 Configurable Macro Cells 24/28 Pins 2.7-3.6V Zero Power SPLD.

TIBPAL20L8-25C : PALs. Low-Power, High-Performance Reduced ICC 105 mA Max fmax: Without Feedback. 33 MHz Min With Feedback. 25 MHz Min tpd. 25 ns Max Direct Replacement for PAL20R6A, PAL20L8A, with at Least 50% Reduction in Power Preload Capability on Output Registers Simplifies Testing Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels.

TIBPAL22VP10-25M : PALs. TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS Functionally Equivalent to the TIBPAL22V10/10A, with Additional Feedback Paths in the Output Logic Macrocell Choice of Operating Speeds: 20 ns Max 25 ns Max Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User.

Virtex-E_Extended_Memory : Virtex-e Extended Memory Field Programmable Gate Array. VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays Fast, Extended Block RAM, 1.8 V FPGA Family 560 Kb and 1,120 Kb embedded block RAM - 130 MHz internal performance (four LUT levels) - PCI compliant 32/64-bit, 33/66-MHz Sophisticated SelectRAM+TM Memory Hierarchy Kb of internal configurable distributed RAM Kb of synchronous internal block.

WATCHDOGTIMER : FPGA/PLD Soft Core. Embedded Risc Microcontroller Core Peripheral. 28-bit Prescaler Programmable Time-out Period Fully Synchronous Protected Turn-off Sequence to 100% Fault Coverage with Scan Test The AVR® embedded RISC microcontroller core is a low power, CMOS 8-bit microprocessor based on AVR RISC architecture. With this core, Atmel supplies a buscompatible Watchdog Timer. The watchdog timer generates a time-out.

ECP2-6 : The LatticeECP2/M family of FPGA devices has been optimized to deliver high performance such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M.

 
0-C     D-L     M-R     S-Z