Details, datasheet, quote on part number: 5962-9952101QYA
Part5962-9952101QYA
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD)
DescriptionUltra37000 CPLD
CompanyCypress Semiconductor Corp.
DatasheetDownload 5962-9952101QYA datasheet
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Features, Applications

Features

In-System ReprogrammableTM (ISRTM) CMOS CPLDs JTAG interface for reconfigurability Design changes do not cause pinout changes Design changes do not cause timing changes High density to 512 macrocells to 264 I/O pins Five dedicated inputs including four clock pins Simple timing model No fanout delays No expander delays No dedicated vs. I/O pin delays No additional delay through PIM No penalty for using full 16 product terms No delay for steering or sharing product terms 3.3V and 5V versions PCI-compatible[1] Programmable bus-hold capabilities on all I/Os Intelligent product term allocator provides: to 16 product terms to any macrocell Product term steering on an individual basis Product term sharing among local macrocells Flexible clocking Four synchronous clocks per device Product term clocking Clock polarity control per logic block Consistent package/pinout offering across all densities Simplifies design migration Same pinout for 3.3V and 5.0V devices Packages to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages

The Ultra37000TM family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. All of the Ultra37000 devices are electrically erasable and InSystem Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAGcompliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming. Ultra37000V 3.3V Devices operating with a 3.3V supply require 3.3V on all VCCO pins, reducing the device's power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming.

Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.

5.0V Selection Guide General Information Device CY37384 CY37512 Speed Bins Device CY37384 CY37512 Device-Package Offering and I/O Count Device CY37512 3.3V Selection Guide General Information Device CY37384V CY37512V Macrocells Dedicated Inputs I/O Pins Speed (tPD) Speed (fMAX) 44Lead TQFP 37 44Lead PLCC 44Lead CLCC 84Lead PLCC 84Lead CLCC 100Lead TQFP 160Lead TQFP 160Lead CQFP 208Lead PQFP 208Lead CQFP 256Lead BGA 352Lead BGA 83 66 Macrocells Dedicated Inputs I/O Pins Speed (tPD) Speed (fMAX)

Shaded areas indicate preliminary speed bins.

Device-Package Offering & I/O Count Device CY37512V 44Lead TQFP 44Lead PLCC 44Lead CLCC 48Lead FBGA 84Lead PLCC 84Lead CLCC 100Lead TQFP 100Lead FBGA 160Lead TQFP 160Lead CQFP 208Lead PQFP 208Lead CQFP 256Lead BGA 256Lead FBGA 352Lead BGA 400Lead FBGA Logic Block The logic block is the basic building block of the Ultra37000 architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram. Product Term Array Each logic block features x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block. The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array. Page of 63

Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations. The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family. An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software--no hand routing is necessary. WarpTM and third-party development packages automatically route designs for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments.


 

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