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Part: CY2410SC-5
Category:
Timing Circuits
Description: Mediaclock
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2410SC-5 datasheet File size : 207 kB
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Datasheet text preview:
CY2410
MPEG Clock Generator with VCXO
Features · Integrated phase-locked loop (PLL) · Low-jitter, high-accuracy outputs · VCXO with analog adjust · 3.3V operation · Pin-for-pin compatible with MK3727 (-1,-4, -5, -6) Advanced Features · Serial programming interface (CY2410-3 only) · Lower drive strength settings (CY2410-4, -6) · Matches nonlinear MK3727 VCXO control curve (CY2410-5, -6) Part Number CY2410-1 CY2410-3 CY2410-4 CY2410-5 CY2410-6 Outputs 1 1 1 1 1 Input Frequency Range 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification 13.5-MHz pullable crystal input per Cypress specification Digital VCXO control Electromagnetic interference (EMI) reduction for standards compliance Drop-in replacement for existing designs Output Frequencies VCXO Control Curve Benefits Highest performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Large ±150 ppm range, better linearity Application compatibility for a wide variety of designs Enables design compatibility Benefits
Other Features Pin-for-pin compatible with MK3727 Serial programming interface Same as CY2410-1 except lower drive strength settings Matches MK3727 nonlinear VCXO Control Curve Same as CY2410-5 except lower drive strength
1 copy of 27 MHz linear 1 copy of 27 MHz linear 1 copy of 27 MHz linear 1 copy of 27 MHz nonlinear 1 copy of 27 MHz nonlinear
CY2410-1,-4,-5,-6 Logic Block Diagram
13.5 XIN OSC XOUT Q VCO P VCXO OUTPUT DIVIDERS 27 MHz
PLL
VDD VSS
CY2410-3 Logic Block Diagram
13.5 XIN XOUT P OSC Q
VCO
OUTPUT DIVIDERS
27 MHz
PLL
Digital VCXO Serial Programming Interface
SCLK SDAT
VDD
VSS
Cypress Semiconductor Corporation Document #: 38-07317 Rev. *B
·
3901 North First Street
·
San Jose, CA 95134 · 408-943-2600 Revised December 5, 2002
CY2410
Pin Configurations
CY2410-1,4,5,6 8-pin SOIC
XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT NC or VSS NC or VDD 27 MHz
XIN VDD SDAT VSS
CY2410-3 8-pin SOIC
1 2 3 4 8 7 6 5 XOUT NC or VSS 27 MHz SCLK
Pin Descriptions for CY2410-1, -4, -5, -6
Name XIN VDD VCXO VSS 27 MHz NC/VDD NC/VSS XOUT
[1]
Pin Number 1 2 3 4 5 6 7 8
Description Reference crystal input Voltage supply Input analog control for VCXO Ground 27-MHz clock output No Connect or voltage supply No Connect or ground Reference crystal output
Pin Description for CY2410-3
Name XIN VDD SDAT VSS SCLK 27 MHz NC/VSS XOUT[1] Pin Number 1 2 3 4 5 6 7 8 Description Reference crystal input Voltage supply Serial data input for DCXO control Ground Serial clock input for DCXO control 27-MHz clock output No Connect or ground Reference crystal output
Pullable Crystal Specifications[2]
Parameter Crystal Accuracy TS CRload Co C0/C1 ESR Name Initial Accuracy at 25°C Temperature Stability Aging Load Capacitance Shunt Capacitance C0/C1 Ratio Equivalent Series Resistance 25 14 7 250 35 Min. Typ. Max. ±20 ±30 ±20 Unit ppm ppm ppm pF pF
Notes: 1. Float XOUT if XIN is externally driven. 2. Reference all other crystal parameters per Ecliptek ECX-5432-13.500M specification.
Document #: 38-07317 Rev. *B
Page 2 of 7
CY2410
Serial Programmable Interface Protocol
The CY2410-3 utilizes a two-wire-interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: start bit; 7-bit device address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit memory address (MA); ACK; 8-bit data; ACK; 8-bit data in MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop bit, as illustrated in Figure 1.
SDA Write 1-bit 1 - b i t Sl av e R/W = 0 ACK 7-bit D e vi ce Address Start Signal 1 -b i t Slave A CK 1- bit Slave A CK Data Valid Transition to next bit
SDAT
tDH SCLK V IH V IL CLKHIGH
tSU
8-bit 8-bit Register Register Data A ddres s Stop Signal
CLKLOW
Figure 2. Data Valid and Data Transition Periods
SDAT
Figure 1. Data Frame Architecture
Data Valid
Data is valid when the clock is HIGH, and may only be transitioned when the clock is low as illustrated in Figure 2.
SCLK
Data Frame
Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3.
START
Transition to next bit
STOP
Figure 3. Start and Stop Frame
t1 t2 CLK 50% 50%
Start Sequence
A start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit (0 for Write), followed by register address (8 bits) and register data (8 bits). See Figure 3.
Figure 4. Duty Cycle Definition; DC = t2/t1
t3 80% CLK 20% t4
Stop Sequence
A stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A stop frame frees the bus for writing to another part on the same bus or writing to another random register address. See Figure 3.
Acknowledge Pulse
During Write mode, the CY2410-3 will respond with an ACK pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the next clock cycle after the eighth bit is shifted in.
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Device Address
The 7-bit device address is 1101001.
Register Address
The 8-bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00HFFH. As you increase the value, the capacitance on the XIN and XOUT pins will increase, thereby decreasing the xtal frequency.
Document #: 38-07317 Rev. *B
Page 3 of 7
CY2410
Absolute Maximum Conditions
Parameter VDD TS TJ Description Supply Voltage Storage Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge
[3]
Min. 0.5 65 VSS 0.3 VSS 0.3 2000
Max. 7.0 125 125 VDD + 0.3 VDD + 0.3
Unit V °C °C V V V
Junction Temperature
Recommended Operating Conditions
Parameter VDD TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency 13.5 Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 Unit V °C pF MHz
DC Electrical Specifications
Parameter IO H IO L IO H IO L CIN II Z fXO VVCXO IVDD Name Output HIGH Current -1,3,5 Output LOW Current -1,3,5 Output HIGH Current -4,6 Output LOW Current -4,6 Input Capacitance Input Leakage Current VCXO pullability range VCXO input range Supply Current +150 0 30 VDD 35 5 Description VOH = VDD 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V VOH = VDD 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 6 6 Typ. 24 24 18 18 7 Max. Unit mA mA mA mA pF µA ppm V mA
AC Electrical Specifications (VDD = 3.3V)[4]
Parameter[4] DC EROR EROF EROR EROF t9 t9 t10 Name Output Duty Cycle Rising Edge Rate -1, -3, -5 Falling Edge Rate -1, -3, -5 Rising Edge Rate -4, -6 Falling Edge Rate -4, -6 Clock Jitter -1, -3, -5 Clock Jitter -4, -6 PLL Lock Time Description Duty Cycle is defined in Figure 4, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 5. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 5. Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 5. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 5. Peak-to-peak period jitter Peak-to-peak period jitter Min. 45 0.8 0.7 0.7 0.7 Typ. 50 1 .4 1 .4 1 .1 1 .1 140 150 3 Max. 55 Unit % V/ns V/ns V/ns V/ns ps ps ms
Notes: 3. Rated for ten years. 4. Not 100% tested.
Document #: 38-07317 Rev. *B
Page 4 of 7
CY2410
Serial Programming Interface Timing Specifications
Parameter fSCL CLKLOW CLKHIGH tSU tDH Frequency of SCLK Start mode time from SDAT LOW to SCLK LOW SCLK LOW period SCLK HIGH period Data transition to SCLK HIGH Data hold (SCLK LOW to data transition) Rise time of SCLK and SDAT Fall time of SCLK and SDAT Stop mode time from SCLK HIGH to SDA HIGH Stop mode to start mode 0.6 1.3 0.6 1.3 0.6 100 0 300 300 Description Min. Max. 400 Unit kHz µS µS µS ns ns ns ns µs µs
Test and Measurement Set-up VDD 0.1 µF OUTPUTS CLK out CLOAD
GND Ordering Information
Ordering Code CY2410SC-1 CY2410SC-1T CY2410SC-3 CY2410SC-3T CY2410SC-4 CY2410SC-4T CY2410SC-5 CY2410SC-5T CY2410SC-6 CY2410SC-6T Package Name S8 S8 S8 S8 S8 S8 S8 S8 S8 S8 Package Type 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Features Linear VCXO control curve Linear VCXO control curve Digital VCXO control Digital VCXO control Lower drive strength (reduced EMI) Lower drive strength (reduced EMI) Matches nonlinear MK3727 VCXO control curve Matches nonlinear MK3727 VCXO control curve Lower drive strength version of CY2410-5 Lower drive strength version of CY2410-5
Document #: 38-07317 Rev. *B
Page 5 of 7
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