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Part: CY2411
Category:
Timing Circuits
-> Clock Buffers
Description: Mpeg With Vcxo
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2411 datasheet File size : 207 kB
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Datasheet text preview:
CY2411
MediaClockTM MPEG Clock Generator with VCXO
Features · Integrated phase-locked loop (PLL) · Low-jitter, high-accuracy outputs · VCXO with analog adjust · 3.3V operation Part Number CY2411-1 Outputs 1 Input Frequency Range 13.5-MHz Pullable Crystal per Cypress Specification Output Frequencies 1 copy of 54 MHz (3.3V) Benefits Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Large ± 150 ppm range, better linearity
Logic Block Diagram
13.5 XIN O SC XOUT Q VCO P VCXO OUTPUT DIVIDER 54 MHz
Pin Configuration
CY2411 8-pin SOIC
XIN AVDD VCXO AVSS 1 2 3 4 8 7 6 5 XOUT VSS 54 MHz VDD
PLL
AVDD VDD
AVSS
VSS
Pin Summary
Pin Name AVDD VDD AVSS VSS XIN VCXO XOUT
[1]
Pin Number 2 5 4 7 1 3 8 6
Pin Description Analog Voltage Supply Output Voltage Supply Analog Ground Output Ground Reference Crystal Input Analog Control for VCXO Reference Crystal Output 54-MHz clock output
54 MHz
Note: 1. Float XOUT if XIN is externally driven.
Cypress Semiconductor Corporation Document #: 38-07193 Rev. *B
·
3901 North First Street
·
San Jose
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CA 95134 · 408-943-2600 Revised December 14, 2002
CY2411
Absolute Maximum Conditions
Parameter VDD TS TJ Description Supply Voltage Storage Temperature Digital Inputs Digital Outputs Referred to VDD Electro-Static Discharge
[2]
Min. 0.5 65 VSS 0.3 VSS 0.3 2000
Max. 7.0 125 125 VDD + 0.3 VDD + 0.3
Unit V °C °C V V V
Junction Temperature
Recommended Operating Conditions
Parameter VDD TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature Max Load Capacitance Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 13.5 0.05 13.5 Min. 3.15 0 Typ. 3.3 Max. 3.45 70 15 13.5 500 Unit V °C pF MHz ms
Pullable Crystal Specifications
Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over Temperature and Aging + 20 0 35 Description Crystal Load Capacitance Min. Typ. 12.4 240 50 70 + 20 + 50 °C ppm ppm Max. Unit pF
DC Electrical Characteristics
Parameter IOH IOL CIN IIZ fxo VVCXO IDD Parameter[3] DC = t2/t1 ER0 EF0 t9 Description Output High Current Output Low Current Input Capacitance Input Leakage Current VCXO Pullability Range VCXO Input Range Supply Current VDD = 3.45V, Cload = 15pF 150 0 15 5 +150 AVDD 20 Conditions VOH = VDD 0.5, VDD = 3.3 V (source) VOL = 0.5, VDD = 3.3 V (sink) Min. 12 12 Typ. 24 24 7 Max. Unit mA mA pF µA ppm V mA
AC Electrical Characteristics (VDD = 3.3V)
Description Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, Cload = 15 pF (see Figure 2) Output Clock Edge Rate, Measured from 80% to 20% of VDD, Cload = 15 pF (see Figure 2) Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 Max. 55 Unit % V/ns V/ns ps
Document #: 38-07193 Rev. *B
Page 2 of 5
CY2411
AC Electrical Characteristics (VDD = 3.3V)
Parameter[3] t10
Notes: 2. Rated for 10 years. 3. Not 100% tested.
Description PLL Lock Time
Conditions
Min.
Typ.
Max. 3
Unit ms
t1 t2
t3 80%
t4
54 MHz
50%
54 MHz
20%
Figure 1. Duty Cycle Definition; DC = t2/t1
Figure 2. Rise and Fall Time Definitions: ER = 0.6 × VDD/t3, EF = 0.6 × VDD/t4
Test Circuit AVDD 0.1 µF OUTPUTS CLK out CLOAD
VDD 0.1 µF GND Ordering Information
Ordering Code CY2411SC-1 CY2411SC-1T Package Name S8 S8 Package Type 8-pin SOIC 8-pin SOICTape and Reel Operating Range Commercial Commercial Operating Voltage 3.3V 3.3V
Document #: 38-07193 Rev. *B
Page 3 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2411
Pin Diagrams
8-lead (150-mil) SOIC S8
51-85066-A
MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07193 Rev. *B
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CY2411
Document Title: CY2411 54-MHz MPEG Clock Generator with VCXO Document Number: 38-07193 REV. ** *A *B ECN NO. 110594 111572 121875 Issue Date 11/07/01 04/30/02 12/14/02 Orig. of Change DSG CKN RBI Description of Change Change from Spec number: 38-00957 to 38-07193 Changed title to "MPEG Clock Generator with VCXO" Added -1 data on pp. 1 and 3 Power up requirements added to Operating Conditions Information
Document #: 38-07193 Rev. *B
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