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Part: CY2412
Category:
Timing Circuits
-> Clock Buffers
Description: Mpeg With Vcxo
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2412 datasheet File size : 207 kB
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Datasheet text preview:
CY2412
MPEG Clock Generator with VCXO
Features · Integrated phase-locked loop (PLL) · Low-jitter, high-accuracy outputs · VCXO with analog adjust · 3.3V operation Benefits Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Large ±150-ppm range, better linearity Enables application compatibility
Part Number CY2412 CY2412-3
Outputs 3 3
Input Frequency Range
Output Frequencies
VCXO Profile
13.5-MHz pullable crystal input per Two 27-MHz outputs, one 54-MHz output (3.3V) Linear Cypress specification 13.5-MHz pullable crystal input per 27 MHz, 13.5 MHz, 54 MHz (3.3V) Cypress specification Linear
Logic Block Diagram
Pin Configuration
CY2412,-3 8-pin SOIC
XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT CLKC CLKB CLKA
CLKC 13.5 XIN OSC XOUT Q
VCO P
OUTPUT DIVIDERS
CLKB
CLKA
VCXO
PLL
VDD
VSS
Cypress Semiconductor Corporation Document #: 38-07227 Rev. *C
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised December 12, 2002
CY2412
Pin Summary
Pin Name XIN VDD VCXO VSS CLKA CLKB CLKB CLKC XOUT[1] 1 2 3 4 5 6 6 7 8 Pin Number Reference Crystal Input Voltage Supply Input Analog Control for VCXO Ground 54-MHz clock output 27-MHz clock output (-1) 13.5-MHz clock output (-3) 27-MHz clock output Reference Crystal Output Pin Description
Pullable Crystal Specifications
Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over Temperature and Aging 0 35 Description Crystal Load Capacitance Min. Typ. 14 240 50 70 ± 20 ± 50 °C ppm ppm Max. Unit pF
Absolute Maximum Conditions
Parameter VDD TS TJ Description Supply Voltage Storage Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge
[2]
Min. 0.5 65 VSS 0.3 VSS 0.3 2
Max. 7.0 125 125 VDD + 0.3 VDD + 0.3
Unit V °C °C V V kV
Junction Temperature
Recommended Operating Conditions
Parameter VDD TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 13.5 500 Min. 3.14 0 Typ. 3.3 Max. 3.47 70 15 Unit V °C pF MHz ms
Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for ten years.
Document #: 38-07227 Rev. *C
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CY2412
DC Electrical Characteristics
Parameter IOH IOL CIN IIZ fXO VVCXO fVBW IDD Description Output High Current Output Low Current Input Capacitance Input Leakage Current VCXO pullability range VCXO input range VCXO input bandwidth Supply Current Sum of Core and Output Current +150 0 DC to 200 35 VDD 5 Test Conditions VOH = VDD 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 Typ. 24 24 7 Max. Unit mA mA pF µA ppm V kHz mA
AC Electrical Characteristics
Parameter[3] DC ER EF t9 t10 Description Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Test Conditions Duty Cycle is defined in Figure 1, 50% of VDD Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15pF See figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See figure 2. Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 100 200 3 Max. 55 Unit % V/ns V/ns ps ms
t1 t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3 80%
t4
CLK
20%
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4
Note: 3. Not 100% tested.
Document #: 38-07227 Rev. *C
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CY2412
Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD
GND
Ordering Information
Ordering Code CY2412SC CY2412SCT CY2412SC-3 CY2412SC-3T Package Name S8 S8 S8 S8 Package Type 8-pin SOIC 8-pin SOICTape and Reel 8-pin SOIC 8-pin SOICTape and Reel Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V
Package Diagram
8-lead (150-mil) SOIC S8
51-85066-A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07227 Rev. *C
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© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2412
Document Title: CY2412 MPEG Clock Generator with VCXO Document Number: 38-07227 REV. ** *A *B *C ECN NO. 110492 112457 116961 121879 Issue Date 10/28/01 03/14/02 08/06/02 12/12/02 Orig. of Change SZV CKN CKN RBI Description of Change Change from Spec number: 38-00898 to 38-07227 Added CY2412-2 to data sheet Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet. Power up requirements added to Operating Conditions Information
Document #: 38-07227 Rev. *C
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