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Part: CY2413
Category:
Timing Circuits
Description: Vcxo & Output Freq. Select
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2413 datasheet File size : 207 kB
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Datasheet text preview:
CY24 13
Set Top Box Clock Generator with VCXO
Features · Low jitter, high accuracy outputs · VCXO with analog adjust · 3.3V Operation with 2.5 V Output Option Part Number CY2413-1 CY2413-2 Outputs 3 2 Input Frequency Range 13.5-MHz pullable Crystal per Cypress Specification 13.5-MHz pullable Crystal per Cypress Specification Benefits Meets critical timing requirements in complex system designs Large ±150 ppm range, better linearity Enables application compatibility Output Frequency Range 13.5-, 27-, 36-, and 54-MHz selectable output frequencies 27-, and 54-MHz output frequencies
Logic Block Diagram CY2413-1
XIN OSC XOUT Q VCO P VCXO
Pin Configuration
LCLK_1
PLL
Output Multiplexer and Dividers
CY2413-1 16-pin TSSOP
XIN VDD AVDD VCXO AVSS VSSL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK_3 NC VSS LCLK_2 VDDL FS0 LCLK_1
LCLK_2 CLK_3
FS0
ROM
FS1 OE
FS1 OE
AVDD
VDD AVSS VSS
VDDL VSSL
Logic Block Diagram CY2413-2
XIN OSC XOUT Q VCO P VCXO
Pin Configuration
CY2413-2 16-pin TSSOP
XIN VDD AVDD VCXO AVSS VSSL NC OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT NC NC VSS LCLK_2 VDDL NC LCLK_1
LCLK_1
PLL
Output Multiplexer and Dividers
L CL K _ 2
VDD
AVDD
AVSS VSS
VSSL
VDDL
OE
Cypress Semiconductor Corporation Document #: 38-07226 Rev. *A
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised December 14, 2002
CY2413
Pin Summary - CY2413-1
Name XIN VDD AVDD VCXO AVSS VSSL FS1 OE LCLK_1 FS0 VDDL LCLK_2 VSS NC CLK_3 XOUT
[1]
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Description Reference Crystal Input Voltage Supply Analog Voltage Supply Input Analog control voltage for VCXO Analog Ground LCLK Ground Frequency Select Output Enable Configurable Clock output 1 at VDDL level Frequency Select LCLK Voltage Supply (2.5V or 3.3V) Configurable Clock output 2 at VDDL level Ground No Connect Configurable Clock output 3 Reference Crystal Output
Frequency Select Table - CY2413-1
FS1 0 0 1 1 F SO 0 1 0 1 Input 13.5 13.5 13.5 13.5 L CLK_ 1 54 13.5 27 27 L CLK_ 2 36 36 54 27 CLK_3 off 13.5 13.5 13.5
Note: 1. Float XOUT if XIN is externally driven
Document #: 38-07226 Rev. *A
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CY2413
Pin Summary CY2413-2
Name XIN VDD AVDD VCXO AVSS VSSL NC OE LCLK_1 NC VDDL LCLK_2 VSS NC NC XOUT[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Voltage Supply Analog Voltage Supply Input Analog control voltage for VCXO Analog Ground LCLK Ground No Connect Output Enable 54-MHz Clock output 1 at VDDL level No Connect LCLK Voltage Supply (2.5V or 3.3V) 27-MHz Clock output 2 at VDDL level Ground No Connect No Connect Reference Crystal Output Description Reference Crystal Input
Pullable Crystal Specifications
Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over temperature and aging 0 Name Crystal Load Capacitance Min. Typ. 14 240 35 70 + 20 + 50 °C ppm ppm Max. Unit pF
Absolute Maximum Conditions
Parameter VDD VDDL TS TJ Description Supply Voltage I/O Supply Voltage Storage Temperature Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL Analog Input referred to AVDD Electro-Static Discharge Soldering Temperature 10 sec
Note: 2. Rated for 10 years.
Min. 0.5 0.5
[2]
Max. 7.0 7.0 100 125 AVDD + 0.3 VDD + 0.3 VDDL +0.3 AVDD + 0.3 235°
Unit V V °C °C V V V V kV °C
65 AVSS 0.3 VSS 0.3 VSSL 0.3 AVSS 0.3 2
Junction Temperature
Document #: 38-07226 Rev. *A
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CY2413
Recommended Operating Conditions
Parameter VDD VDDL AVDD TA CLOAD CLOAD fREF Pmax tPU Description Operating Voltage Operating Voltage Analog Operating Voltage Ambient Temperature Max. Load Capacitance VDD/VDDL=3.3V Max. Load Capacitance VDDL=2.5V Reference Frequency Max. Output Power Dissipation Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 13.5 115 500 Min. 3.0 2.375 3.0 0 Typ. 3.3 2.5 3.3 Max. 3.6 2.625 3.6 70 15 15 Unit V V V °C pF pF MHz °C/W ms
DC Electrical Characteristics
Parameter[3] IOH IOL IOH IOL VIH VIL CIN IIZ fXO VVCXO fVBW IVDD IVDDL3 IVDDL2 Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current VCXO pullability range VCXO input range VCXO input bandwidth Supply Current Supply Current Supply Current AVDD/VDD Current VDDL Current (VDDL=3.6V) VDDL Current (VDDL=2.625V) 10 5 5 Description VOH = VDD 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VOH = VDDL 0.5, VDDL = 2.5V VOL = 0.5, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD Frequency Select and OE Pins Frequency Select and OE Pins 150 0 DC to 200 35 15 12 5 +150 AVDD Min. 12 12 8 8 0.7 0.3 7 Typ. 24 24 16 16 Max. Unit mA mA mA mA VDD VDD pF µA ppm V kHz mA mA mA
Document #: 38-07226 Rev. *A
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CY2413
AC Electrical Characteristics
Parameter[3] DC t3 t3 t4 t4 t9 t10 Name Output Duty Cycle Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 2, 50% of VDD Output Clock Rise Time, 80% 20% of VDD/VDDL, VDDL = 3.3V Output Clock Rise Time, 80% 20% of VDDL = 2.5V Output Clock Fall Time, 80% 20% of VDD/VDDL, VDDL = 3.3V Output Clock Fall Time, 80% 20% of VDDL = 2.5V Peak to Peak period jitter Measured from VDD = 3.0V Min. 45 0.8 0.6 0.8 0.6 Typ. 50 1.4 1.2 1.4 1.2 250 450 3 Max. 55 Unit % V/ns V/ns V/ns V/ns ps ms
Note: 3. Not 100% tested
Document #: 38-07226 Rev. *A
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