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Part: CY2DL814ZC
Category:
Timing Circuits
-> Backplane Interface
Description: High Performance Clock And Data Buffers With Low Voltage Operations
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2DL814ZC datasheet File size : 207 kB
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Datasheet text preview:
ComLinkTM Series CY2DL814
1:4 Clock Fanout Buffer
Features
· · · · Low-voltage operation VDD = 3.3V 1:4 Fanout Single-input configurable for -- LVDS, LVPECL, or LVTTL -- Four differential pairs of LVDS outputs Drives 50- or 100-ohm load (selectable) Low input capacitance Low output skew Does not exceed Bellcore 802.3 standards Operation at 350 MHz 700 Mbps Low propagation delay Typical (tpd < 4 ns) Industrial versions available Packages available include TSSOP/SOIC
Description
The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic. The Cypress CY2DL814 fanout buffer features a single LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS output pairs. Designed for data-communication clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output driver's support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.
· · · · · · · ·
Block Diagram
Pin Configuration
E N1 E N2 Q1A Q1B
EN1 CONFIG CNTRL VDD GND IN+ INEN2
Q3A Q3B
I N+ I NLVDS / LVPECL / LVTTL C O N FI G
Q2A Q2B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B
16-pin TSSOP/SOIC
Q4A Q4B CNT R L
O UT P U T
LVDS
Cypress Semiconductor Corporation Document #: 38-07057 Rev. *A
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised December 14, 2002
CY2DL814
ComLinkTM Series CY2DL814
Pin Description
Pin Number 6,7 3 Pin Name IN+, IN CNTRL Pin Standard Interface Configurable LVTTL/LVCMOS Description Differential input pair or single line. LVPECL default. See config below. Converts into a High drive driver from a standard LVDS. Standard drive (logic = 0) B/High drive/Bus (logic = 1) Converts inputs (IN+/IN), (EN, EN#) from the default LVPECL/LVDS (logic = 0) To LVTTL/LVCMOS (logic = 1) Enable/disable logic. See Table 1 below for details. Differential outputs.
2
CONFIG
LVTTL/LVCMOS
1,8 16,15,14,13 12,11,10,9
EN1, EN2 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B VDD
LVTTL/LVCMOS LDVS
4 5
POWER POWER
Positive supply voltage Ground
GND
Maximum Ratings[1][2]
Storage Temperature: ........ 65°C to + 150°C Ambient Temperature:.. 40°C to +85°C Supply Voltage to Ground Potential (Inputs and VCC only)...... 0.3V to 4.6V Supply Voltage to Ground Potential Table 1. EN1 EN2 Function TableDifferential Input Mode Enable Logic EN1 H H X X L EN2 X X L L H IN+ H L H L X Input IN L H L H X QnA H L H L Z Outputs QnB L H L H Z (Outputs only) ....... 0.3V to VDD + 0.3V DC Input Voltage .. 0.3V to VDD + 0.3V DC Output Voltage......... 0.3V to VDD + 0.9V Power Dissipation........ 0.75W
Table 2. Output Drive Control for Standard and Bus/B/High Drive B CNTRL Pin 3 Binary Value 0 1 Drive STD Standard High Drive/Bus/B Impedance 100 ohm 50 ohm 100 ohm 50 ohm Output Voltage Value V0 = Voutput V = 1/2 * V0 V = 2 * V0 V = V0
Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07057 Rev. *A
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ComLinkTM Series CY2DL814
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS CONFIG Pin 2 Binary Value 1 0
Input Receiver Family LVTTL in LVCMOS LVDS LVPECL
Input Receiver Type Single-ended, Non-inverting, Inverting, Void of Bias Resistors Low-voltage Differential Signaling Low-voltage Pseudo (Positive) Emitter Coupled Logic
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground VCC Ground VCC IN Pin 7 IN+ Pin 6 IN Pin 7 IN+ Pin 6 IN+ Pin 6 IN Pin 7 IN+ Pin 6 IN Pin 7 Table 5. Power Supply Characteristics Parameter ICCD Description Dynamic Power Supply Current Test Conditions VDD = Max. Input toggling 50% Duty Cycle, Outputs Open VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL=100 MHz Min. Typ. 1.5 Max. 2 .0 Unit mA/MHz Input Invert Input True Input Invert Input True Input Logic Output Logic Q Pins, Q1A or Q1
IC
Total Power Supply Current
90
100
mA
Table 6. D.C Electrical Characteristics: 3.3VLVDS Input Parameter VID VIC VIH VIL IIH IIL II Description Magnitude of Differential Input Voltage Common-mode of Differential Input Voltage IVIDI (min. and max.) Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(max.) VIN = VDD VIN = VSS ±10 ±10 Config/Cntrl Pins Conditions Min. 100 IVIDI/2 2 0.8 ±20 ±20 ±20 Typ. Max. Unit 600 2.4(IVIDI/2) mV V V V µA µA µA
Table 7. D.C Electrical Characteristics: 3.3VLVPECL Input Parameter VID VCM IIH IIL II Description Differential Input Voltage p-p Common-mode Voltage Input High Current Input Low Current Input High Current VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VIN = VDD VIN = VSS Conditions Guaranteed Logic High Level Min. 400 1.65 ±10 ±10 Typ. Max. 2600 2.25 ±20 ±20 ±20 Unit mV V µA µA µA
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ComLinkTM Series CY2DL814
Table 8. D.C Electrical Characteristics: 3.3VLVTTL/LVCMOS Input Parameter VIH VIL II H II L II VIK VH Parameter I VOD I VOC(SS) Delta VOC(SS) VOC(PP) IO S Voh Vol Parameter Rise Time Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Description Steady-state common-mode output voltage Change in VOC(SS) between logic states Peak to peak common mode output voltage Output short circuit Output voltage high Output voltage low Description Conditions RL = 100 ohm QA = 0V or QB = 0V RL = 100 ohm 925 50 3 Conditions RL = 100 ohm Conditions Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = 18 mA 0.7 80 Min. 0.25 Typ. Max. 0 .45 226 50 150 20 1475 VIN = 2.7V VIN = 0.5V Min. 2 0.8 1 1 20 1.2 Typ. Max. Unit V V µA µA µA V mV Unit V mV mV mV mA mV mV
Table 9. D.C Electrical Characteristics: 3.3VLVDS OUTPUT Differential output voltage p-p VDD = 3.3V, VIN = VIH, or VIL
Table 10. AC Parameters Min. Typ. Max. Unit 1.4 ns Pin control (pin 3) logic is "FALSE" CL10 pF defaulting to 100 ohm output drivers. RL and CL to GND 3 CL = Cintrinsic and Cexternal Differential 20% to 80% Pin control (pin 3) logic is "True" defaulting to 50 ohm output drivers. Differential 20% to 80% CL10 pF RL and CL to GND 3 CL = Cintrinsic and Cexternal
Fall Time Rise Time RL = 50 ohm Output boost 350
1.4 600
ns ps
Fall Time Table 11. AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = 40°C to +85°C) Parameter tPLH tPHL Tpd TPe Tpd tSK(0) tSK(p) tSK(t) Description Propagation Delay Low to High Propagation Delay High to Low Propagation Delay Enable (EN) to functional operation Functional operation to Disable Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHLtPLH) Package Skew: Skew between outputs of different VID = 100 mV packages at the same power supply voltage, temperature and package type. Same input signal level and output load. 0.2 Conditions VOD = 100 mV Min. 3 3 3
350 Typ. 4 4 4
600
ps Unit ns ns ns ns ns ns ns
Max. 5 5 5 6 5 0.2
IN [+,-] to Q[A,B] Data and Clock Speed
IN [1,2] to Q[A,B] Control Speed
Q[A,B] Output Skews
1
ns
Document #: 38-07057 Rev. *A
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ComLinkTM Series CY2DL814
Table 12. High Frequency Parametrics Parameter Fmax Fmax(20) Description Maximum frequency VDD = 3.3V Maximum frequency VDD = 3.3 V Conditions 50% duty cycle tW(5050) Standard Load Circuit. 20% duty cycle tW(5050) LVPECL Input VIN = VIH(Max.)/VIL(Min.) VOUT = VOH(Min.)/VOL (Max.) (Limit) LVPECL Input VIN = VIH(Max.)/VIL(Min.) F= 100 MHz VOUT = VOH(Min.)/VOL(Max.)(Limit)
A
P ulse G en e r at o r
TP A
Min.
Typ.
Max. 400 200
Unit MHz MHz
TW
Minimum pulse VDD = 3.3 V
1
ns
10pF B
50
TP C
50
TP B
Sta n da rd Termination
V 1A
1.2 V CM
1 .4 V
0V Differential
V 1B V 0Y
1.2 V CM
1 .0 V 1 .4 V
0V Differential
V 0Z
T PLH TP HL
1 .0 V
80% 0V Differential V0Y - V0Z 20%
tR
tF
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6]
A
Pulse Generator
TPA
50
TPC
B
50
TPB
VOC
VOD
Standard Termination
VI(A) VI(B)
2.0V 1.6V
Next Device
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3,4,5,6]
Notes: 3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. 4. RL= 50 ohm ± 1% Zline = 50 ohm 6". 5. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD- 2.
Document #: 38-07057 Rev. *A
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