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Part: CY2DL818ZCT
Category:
Description: 1:8 Clock Fanout Buffer
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2DL818ZCT datasheet File size : 207 kB
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CY2DL818
1:8 Clock Fanout Buffer
Features
· · · · · · · · · · · · · Low voltage operation VDD = 3.3V 1:8 fanout Single-input-configurable for LVDS, LVPECL, or LVTTL 8 pair of LVDS Outputs Drives either a 50-ohm or 100-ohm load (selectable) Low input capacitance Low output skew Low propagation delay Typical (tpd 350 MHz 700 Mbps
Description
This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic. The Cypress CY2DL818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVDS output pairs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL818 has configurable input and output functions. The input can be selectable for LVCMOS/LVTTL, LVPECL, or LVDS signals, while the output driver's support standard and high-drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.
Block Diagram
37 36
Pin Configuration
Q1A Q1B
35 34
Q2A Q2B
(LVPECL / LVDS / LVTTL) 10 11 28 27 31 30
Q4A Q4B Q5A Q5B Q6A Q6B
INPUT A INPUT B
InConfig
6
26 25
24 23
VDD GND INPUT A INPUT B GND VDD VDD VDD VDD VDD GND GND
CY2DL818
INPUT
33 32
Q3A Q3B
GND VDD VDD VDD VDD InConfig CNTRL
Q7A Q7B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND
38 pin TSSOP
22 21
Q8A Q8B
CNTRL
7
OUTPUT
(LVDS)
Cypress Semiconductor Corporation Document #: 38-07058 Rev. **
·
3901 North First Street
·
San Jose
·
CA 95134 · 408-943-2600 Revised May 28, 2002
CY2DL818
Pin Description
Pin Number 1, 9,12, 18,19,20,38 2,3,4,5,8, 13 14,15,16,17,29 10,11 Pin Name GND VDD Input A, Input B(#) Pin Standard Interface POWER Ground POWER Power Supply Pin Description
37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 6
Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, Q6A, Q6B, Q7A, Q7B, Q8A, Q8B InConfig
Default: LVPECL / LDVS Differential input pair or single line. Optional: LVTTL/LVCMOS LVPECL/LVDS default. See InConfig below. single pin. LDVS Differential Outputs
LVTTL / LVCMOS
7
CNTRL
LVTTL / LVCMOS
Converts inputs from the default LVPECL/LVDS (logic = 0) To LVTTL/LVCMOS (logic = 1) "default pull-up" See Figure 6 and Figure 7 for additional information Converts into a high-speed driver. Logic = 0 = 100 ohm Logic = 1 = 50-ohm "default pull-up" See Figure 7 for additional Information
Output Drive Control for Standard and Bus/B/Hi-Drive CNTRL Pin 7 Binary Value 0 1 Drive STD Standard Hi-drive/Bus/B Impedance 100 Ohms 50 Ohms 100 Ohms 50 Ohms Output Voltage Value VO = Voutput V = 1/2 * VO V = 2 * VO V = VO
Input Receiver Configuration for Differential or LVTTL/LVCMOS InCONFIG Pin 6 Binary Value 1 0 Input Receiver Family LVTTL in LVCMOS LVDS LVPECL Input Receiver Type Single-ended non-inverting, inverting, void of bias resistors. Low-voltage differential signaling Low-voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal Input Condition Input B (-) Pin 11 Input A (+) Pin 10 Input B (-) Pin 11 Input A (+) Pin 10 Input A (+) Pin 10 Input B (-) Pin 11 Input A (+) Pin 10 Input B (-) Pin 11 LVTTL/LVCMOS INPUT LOGIC Input Logic Input Input Bar Input Input Bar Input Input Bar Input Input Bar Output Logic Q Pins, Q1A or Q1 Input Input Bar Input Bar Input Input Input Bar Input Bar Input Min. Typ. Max. 0.40 40 0.5 80 Unit mA/MHz mA
Ground VCC Ground VCC
Power Supply Characteristics Parameter ICCD IC Description Test Conditions Dynamic Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open Total Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 100 MHz
Document #: 38-07058 Rev. **
Page 2 of 8
CY2DL818
Maximum Ratings[1]
Storage Temperature: ........ 65°C to + 150°C Ambient Temperature:.. 40°C to +85°C Supply Voltage to Ground Potential (Inputs and VCC only)...... 0.3V to 4.6V Supply Voltage to Ground Potential (Outputs only) ....... 0.3V to VDD + 0.3V DC Input Voltage .. 0.3V to VDD + 0.3V DC Output Voltage......... 0.3V to VDD + 0.9V Power Dissipation........ 0.75W
D.C Electrical Characteristics: 3.3VLVDS Input
Parameter VID V IC VIH VIL II H II L II Description Magnitude of Differential Input Voltage Common-mode of Differential Input VoltageIVIDI (min. and max.) Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max VDD = Max VDD = Max, VIN = VDD(max.) InConfig/Cntrl Pins VIN = VDD VIN = VSS Conditions Min. 100 2 0.8 ±10 ±10 ±20 ±20 ±20 Typ. Max. Unit 600 mV V V V uA uA uA
IVIDI/2 2.4 (IVIDI/2)
D.C Electrical Characteristics: 3.3VLVPECL Input
Parameter
I VID I
Description Differential input voltage p-p Common-Mode Voltage Input High Current Input Low Current VDD = Max VDD = Max
Conditions Guaranteed Logic High Level VIN = VDD VIN = VSS
Min. 400 1.65
Typ.
Max. 2400 2.25
Unit mV V uA uA
VCM IIH IIL
±10 ±10
±2 0 ±2 0
D.C Electrical Characteristics: 3.3VLVTTL/LVCMOS Input
Parameter Description Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Input Hysteresis Conditions Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max VDD = Max VDD = Max., VIN = VDD(Max) VDD = Min., IIN = -18mA 0.7 80 VIN = 2.7V VIN = 0.5V Min. 2 0.8 1 1 20 1.2 Typ. Max. Unit V V uA uA uA V mV
V IH V IL IIH IIL II V IK VH
D.C Electrical Characteristics: 3.3VLVDS OUTPUT
Parameter I VOD I Risetime Falltime Risetime Falltime IOS VOH VOL Description Differential Output Voltage p-p Pin Control (pin 7) logic is "FALSE" defaulting to 100-ohm output DIfferential 20% to 80% Pin Control (pin 7) logic is "TRUE" setting 50-ohm output drivers differential 20% to 80% Output Short Circuit Output Voltage high Output Voltage low Conditions VDD = 3.3V, VIN = VIH or VIL CL 10 pF RL and CL to GND CL = Cintrinsic and Cexternal See Figure 3 CL 10 pF RL and CL to GND CL = Cintrinsic and Cexternal See Figure 3 RL = 100 ohm Min. 0.25 800 800 350 RL = 50 ohm 350 Typ. Max. 0.55 1500 1500 600 600 10 1550 925 Unit V ps ps ps ps mA mV mV
DOUT = 0V or DOUT- = 0V RL = 100 ohm
Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Document #: 38-07058 Rev. **
Page 3 of 8
CY2DL818
AC Switching Characteristics @ 3.3 V VDD = 3.3V ±5%, Temperature = 40°C to +85°C
Parameter tPLH tPHL tSK(0) tSK(p) tSK(t) Description Propagation Delay Low to High Propagation Delay High to Low Output Skew: Skew between outputs of the same package (in phase) Pulse Skew: Skew between opposite transitions of the same output (tPHL tPLH) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. 200 1.6 Conditions Min. Typ 4.5 4.5 200 Max Unit nS nS pS pS nS
High Frequency Parametrics
Parameter Fmax Description Maximum frequency VDD = 3.3V Deterministic Jitter Conditions 50% duty cycle tW(50-50) Standard Load Circuit. LVDS VID = 100mV 50% duty cycle tW(50-50) Standard Load Circuit. LVDS VID = 100mV 50 Min. Typ Max 400 Unit MHz
Dj
pS
I dd @ 25°C I dd (mA) vs. Input Freq. (MHz)
2 00 1 80 1 60 1 40 Hig h or B Drive Curves 1 20 1 00 80 60 St an dar d Drive Curves 40 20 0 40 1 40 24 0 34 0 440 5 40
Idd (mA)
Input Freq. (MHz)
LD 3.135 LD 3.3 LD 3.465 HD 3.135 HD 3.3 HD 3.465
Figure 1. IDD Current vs. Frequency in Low Drive and High Drive
Document #: 38-07058 Rev. **
Page 4 of 8
CY2DL818
A
P ulse G en e r at o r
TP A
10pF B
50
TP C
50
TP B
Sta n da rd Termination
V 1A V 1B V 0Y V 0Z
T PLH TP HL
80% 0V Differential V0Y - V0Z 20%
1 .4 V
0V Differential
1 .0 V 1 .4 V
0V Differential
1 .0 V
tR
tF
Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5]
A
P u ls e G e n e ra to r
TPA
50
TP C
B
50
TP B
VOC
VOD
S t a n d a r d T e r m in a t io n
V I( A ) V I( B ) V o c (p p )
1 .4 0 V 1 .0 V
N e x t D e v ic e
VDD
V o c (s s )
Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5]
Notes: 2. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF 1 nS; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 nS. 3. RL = 50 ohm/100 ohm ± 1%. 4. CL includes instrumentation and fixture capacitance within 6 mm of the DUT. 5. TPA and B are used for prop delay and Rise/Fall Measurements. TPC is used for VOC measurements only and otherwise connected to VDD 2.
Document #: 38-07058 Rev. **
Page 5 of 8
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