|
|
Part: CY2DP3110AIT
Category:
Timing Circuits
-> Backplane Interface
Description: High Performance Clock Distribution Device
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2DP3110AIT datasheet File size : 207 kB
Request For quote: Find where to buy CY2DP3110AIT
Datasheet text preview:
PRELIMINARY
FastEdgeTM Series CY2DP3110
1 of 2:10 Differential Fanout Buffer
Features
· Ten ECL/PECL differential outputs · Two ECL/PECL and HSTL differential or single-ended inputs · Hot-swappable/-insertable · 35-ps output-to-output skew (typical) · 100-ps device-to-device skew (typical) · Less than 10-pS intrinsic jitter · 400-ps propagation delay (typical) · Operation from DC to above 1.5 GHz · PECL and HSTL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V · ECL mode supply range: VEE = 2.375V to 3.465V with VCC = 0V · Industrial temperature range: 40°C to 85°C · 32-pin TQFP package · Pin-compatible with MC100{EP}{ES6}{LVEP}111 · Temperature compensation as 100K ECL
Description
The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 3.0 GHz. The device features two differential input paths which are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3110 may function not only as a differential clock buffer but also as a signal level translator and fanout an HSTL single-ended signal to 10 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA or CLKB inputs and bypassed to ground via a 0.01-µF capacitor. Since the CY2DP3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high-precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3110 delivers consistent, guaranteed performance over differing platforms.
Block Diagram
Pin Configuration
VBB
CLKA CLKA# CLKB CLKB#
VCC
Q2 Q2# 0 Q3 Q3# Q4 Q4# Q5 Q5#
VCC
1
VCC CLK_SEL CLKA CLKA# VBB CLKB CLKB# VEE
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
Q1 Q1#
VCCO Q0 Q0# Q1 Q1# Q2 Q2# VCCO
Q0 Q0#
CY2DP3110
24 23 22 21 20 19 18 17
Q3 Q3# Q4 Q4# Q5 Q5# Q6 Q6#
CLK_SEL
Q6 Q6# Q7 Q7# Q8 Q8# Q9 Q9#
Cypress Semiconductor Corporation Document #: 38-07469 Rev. *B
·
3901 North First Street
·
VCCO Q9# Q9 Q8# Q8 Q7# Q7 VCCO
9 10 11 12 13 14 15 16
San Jose, CA 95134
· 408-943-2600 Revised June 10, 2003
PRELIMINARY
Pin Description
Pin 3,4 6,7 2 31,29,27,24,22,20,18,1 5,13,11 30,28,26,23,21,19,17,1 4,12,10 5 8 1,9,16, 25,32 Control CLK_SEL 0 0 1 Default condition (no connection to the pin) Name I/O
[1]
FastEdgeTM Series CY2DP3110
Type ECL/PECL HSTL
Description Default differential clock input pair. Alternate differential clock input pair.
CLKA, CLKA# I,PD I,PC CLKB, CLKB# CLK_SEL Q[0-9] Q#[0-9] VBB[3] VEE[2] VCC
I,PD I,PC I,PD O,O E O,OE O PWR +PWR
ECL/PECL Pull-down, selects between CLKA; pull-up for CLKB signals. ECL/PECL True output. [mandatory RL for waveform generation] ECL/PECL Complement output. [mandatory RL for waveform generation] Bias Power Power Reference voltage output for single-ended ECL or PECL operation. Power supply, negative connection. Power supply, positive connection.
Operation
CLKA, CLKA# input pair is active. CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations. CLKB, CLKB# input pair is active. CLKB can be driven by HSTL-0compatible signals with respective power configurations.
Governing Agencies
The following agencies provide specifications that apply to the CY2DP3110. The agency name and relevant specification is listed below. Agency Name JEDEC JESD 51 (Theta JA) JESD 8-6 (HSTL) JESD 8-2 (ECL) JESD 65-A (skew,jitter) 1596.3 (Jitter specs) 94 (Flammability rating) 883E Method 1012.1 (Thermal Theta JC) Specification
IEEE UL Mil-Spec
Notes: 1. In the I/O column, the following notation is used: I = Input, O = Output, PD = Pull-down, PU = Pull-up, PC = Pull Center, OE = Open Emitter and PWR = Power. 2. In ECL mode (negative power supply mode), VEE is either 3.3V or 2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V.
Document #: 38-07469 Rev. *B
Page 2 of 13
PRELIMINARY
Table 1. Absolute Maximum Ratings
Parameter VCC VCC VBB IBB VTT VIN VOUT LUI TS TA ØJc ØJa ESDh MSL GATES FLM Description Supply Voltage Operating Voltage Output Reference Voltage Output Reference Current Output Termination Voltage Input Voltage Output Voltage Latch Up Immunity Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Flammability Rating Assembled Die Relative to VCC Relative to VCC Functional Non-functional Functional Functional Functional 65 40 40 0.3 0.3 Conditions Non-functional Functional Relative to VCC Relative to VBB Min. 0.3 2.5 5%
FastEdgeTM Series CY2DP3110
Max. 4.6 3.3 + 5% VCC 1.220 200 VCC 2 VCC + 0.3 VCC + 0.3 300 +150 +85 60 100 2000 50 V0
Unit VDC VDC VDC uA VDC VDC VDC mA °C °C °C/W °C/W Volts N.A. Each N.A.
VCC 1.620
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
PECL/HSTL DC Specifications (VCC = 2.5V ± 5%/VCC = 3.3 V ± 5%,VEE = GND, Temp. = 40°C 85°C)
Parameter VIL VIH II N VPP VCMR II N VDIF VX II N VOL Description Input Voltage, Low Input Voltage, High Input Current
[4]
Conditions Define VCC and Load Current VIN = VINLMIN or VIHMAX Differential Operation Differential Operation VIN = VILMIN = VIHMAX
Min. VCC 1.945 VCC 1.165
Typ.
Max. VCC 1.625 VCC 0.88 |150|
Unit V V uA
Clock Input Pair CLKA, CLKA (PECL Differential Signals) Differential Input Voltage[5] Differential Crosspoint Voltage[6] Input Current[4] Differential Input Voltage[7] Differential Crosspoint Voltage[8] Input Current VIN = VX ± 0.2V 0 .1 1 .2 1 .3 VCC |150| V V uA
Clock Input Pair CLKB, CLKB (HSTL Differential Signals) 0.4 0.68 1 .9 0.9 |150| V V uA
PECL Outputs Q0Q9, Q0Q9 (PECL Differential Signals) IOL = 5 mA[9] Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% Output High Voltage IOH = 30 mA[9] V VCC 1.945 VCC 1.695 VCC 1.945 VCC 1.695 VCC 1.2 VCC 0.895 VCC 1.5 VCC 1.3
VOH
VCC 0.7 V Notes: 4. Inputs have internal pull-up/pull-down or biasing resistors that affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality. 8. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 9. Equivalent to a termination of 50 to VTT.
Document #: 38-07469 Rev. *B
Page 3 of 13
PRELIMINARY
Parameter Description
[11]
FastEdgeTM Series CY2DP3110
Min. Typ. Max. Unit
PECL/HSTL DC Specifications (VCC = 2.5V ± 5%/VCC = 3.3 V ± 5%,VEE = GND, Temp. = 40°C 85°C) (continued)
Conditions Supply Current and VBB IEE
Maximum Quiescent Supply VEE pin Current without Output Termination Current[10] Output Reference Voltage Internal Pull-up Current Internal Pull-down Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Output Impedance IBB = 200 uA[14] VCC 1.620
130
mA
VBB IPUP IPDWN CIN COUT LIN ZOUT
VCC 1.220
V mA. mA. pF pF
1
nH
ECL DC Specifications (VEE = 2.5V ± 5% or VEE = 3.3 V± 5%, VCC = GND, TA = 40°C to 85°C)
Parameter VIL VIH II N VPP VCMR II N VOH VOL Description Input Voltage, Low Input Voltage, High Input Current[12] Define VCC and Load Current VIN = VIL or Vin = VIH 0 .1 VEE + 1.2 Conditions Min. 1.945 1.165 Typ. Max. 1.625 0.880 |150| Unit V V uA
Clock Input Pair CLKA, CLKA (ECL Differential Signals) Differential Input Voltage[13] Differential Operation Differential Crosspoint Voltage[14] Input Current[12] Differential Operation VIN = VIL or VIN = VIH
[15]
1 .3 0V |150|
V V uA
ECL Outputs Q0Q9, Q0Q9 (ECL Differential Signals) Output High Voltage Output Low Voltage VEE = 2.5V ± 5% VEE = 3.3V ± 5% IOL = 5 ma
IOH = 30 mA[16]
[16]
1.2 1.945 1.945 1.695 1.695
0.7 1.3 1.5
V V V
Supply Current and VBB IEE Maximum Quiescent Supply VEE Pin Current without Output Termination Current[17] Output Reference Voltage IBB = 200 uA 1.525 130 mA
VBB
1.325
V
Table 2. Timing Specifications
Parameter TTB Dj Description Total Timing Budget Deterministic/Intrinsic Jitter Conditions 500-MHz 50% Duty Cycle Standard Load 500-MHz 50% Duty Cycle Standard Load Min. Typ. Max. TBD 1 Unit ps ps r.m.s.
Notes: 10. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE orICC = (number of differential output pairs used) x (VOH VTT)/Rload + (VOL VTT)/Rload +IEE. 11. VBB is limited to VCC of 3.3V only. See note 20. 12. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 13. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality 14. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 15. Standard ECL down to 2.5V, Cypress part operates down to 3.3V 16. Equivalent to a termination of 50 to VTT. 17. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH VTT)/Rload + (VOL VTT)/Rload +IEE.
Document #: 38-07469 Rev. *B
Page 4 of 13
PRELIMINARY
Table 3. Jitter
0000 0101 0100 1100 1100 1100 0111 0001 1100 0111 0101 PRBS 44 bit (9 44-bit Binary streams before loopback) Freq (MHz) 270.00 333.00 500.00 550.00 500 Neg Max (ps) 0.117 0.471 0.261 0.26 0.136 Pos Max (ps) 0.16 0.44 0.276 0.232 CLOCK 0.109 0.245 Peak-Peak (ps) 0.277 0.911 0.537 0.492
FastEdgeTM Series CY2DP3110
R.M.S (ps) 0.116 0.101 0.065 0.61 0.059
AC Specifications ([ECL:VEE = 3.3 VDC ± 5% or VEE= 2.5V±5%, VCC = GND] or [HSTL/PECL:VCC = 3.3V ± 5% or VCC
= 2.5V ±5%, VEE = GND] Temp. = 40°C to 85°C) [18] Parameter VPP VCMR FCLK TPD Description Differential Input Voltage[19] Differential Crosspoint Input Frequency[21] Voltage[20] Conditions Differential Operation Differential Operation 50% duty cycle Standard load 280 400 Min. 0.1 VEE+1.2 Typ. Max. 1.3 0V 2200 650 Unit V V MHz ps
Clock Input Pair CLKA, CLKA (PECL or ECL Differential Signals)
Propagation Delay CLKA or CLKB to 660-MHz 50% Duty Cycle Standard Q0Q9 Pair Load Differential Operation Differential Input Voltage[22] Differential Crosspoint Voltage[23] Input Frequency Propagation Delay CLKA or CLKB to <1-GHz Differential Q0Q9 Pair Differential Output Voltage (Peak-to-Peak) Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz fo < 1.5 GHz fo < 2.7 GHz 660-MHz 50% Duty Cycle Standard Load Differential Operation Duty Cycle Standard Load Differential Operation Standard Load Differential Operation
Clock Input Pair CLKB, CLKB (HSTL Differential Signals) VDIF VX FCLK TPD 0.4 0.68 1.9 0.9 2200 280 400 750 V V MHz ps
ECL Clock Outputs (Q09, Q09) (Differential) Vo(P-P) V 0.45 0.4 0.375 TBD TBD 50 500 1 50 0.3 ps ps ps ps ns
tsk(o) tsk(PP) tJIT(CC) tsk(P) tr, tf
Output-to-Output Skew
Output-to-Output Skew (part-to-part) 660-MHz 50% Duty Cycle Standard Load Differential Operation Output Cycle-to-Cycle Jitter (Intrinsic) RMS Output Pulse Skew[24] Output Rise/Fall time 500-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Differential 20% to 80%
18. AC characteristics apply for parallel output termination of 50 to VTT. 19. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 20. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 21. The CY2DP3110 is fully operational up to 1.5GHz with full PECL swing. Reduced swing up to 2.2 GHz. 22. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew 23. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. 24. Output pulse skew is the absolute difference of the propagation delay times: | tPLH tPHL |.
Document #: 38-07469 Rev. *B
Page 5 of 13
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
|
|
|
