|
|
Part: CY2DP3120
Category:
Timing Circuits
-> Backplane Interface
Description: High Performance Clock Distribution Device
Company: Cypress Semiconductor Corp.
Datasheet: Download CY2DP3120 datasheet File size : 207 kB
Request For quote: Find where to buy CY2DP3120
Datasheet text preview:
PRELIMINARY
FastEdgeTM Series CY2DP3120
1:20 Differential Clock Buffer/Driver
Features
· Twenty ECL/PECL differential outputs · Two ECL-/PECL-/HSTL-compatible differential clock inputs · Hot-swappable/-insertable · 50-ps output-to-output skew · 500-ps device-to-device skew · Less than 10-ps intrinsic jitter · < 500-ps propagation delay (typical) · Operation from DC to 1.5 GHz · PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V · ECL mode supply range: VEE = 2.375V to 3.465V with VCC = 0V · Industrial temperature range: 40°C to 85°C · 52-pin 1.4-mm TQFP package · Temperature compensation like 100K ECL
Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device is fully differential and features two reference input buffers. The CY2DP3120 may function not only as a differential clock buffer but also as a signal level translator and fanout distributing a single-ended signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for an ECL/PECL/HSTL single-ended or differential. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single ended input that might have a different self bias point. Since the CY2DP3120 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3120 delivers consistent, guaranteed performance over differing platforms.
Block Diagram
Pin Configuration
CLKA CLKA#
VEE
VCC
0
VEE VCC
Q0 Q0#
VCCO VCC CLK_SEL CLKA CLKA#
52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 38 2 37 3 4 5 6 7 8 9 10 11 12 36 35 34
VCCO
Q0#
Q1#
Q2#
Q3#
Q4#
Q5#
Q0
Q1
Q2
Q3
Q4
Q5
Q6 Q 6# Q7 Q 7# Q8 Q 8# Q9 Q 9# Q 10 Q 10# Q 11 Q 11# VCCO
CLKB CLKB#
VEE VEE
1
Q19 Q19# VBB
VBB CLKB CLKB# VEE Q19# Q19 Q18# Q18
C Y 2 D P 31 20
33 32 31 30 29 28
CLK_SEL
VEE
13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO Q17# Q16# Q15# Q14# Q13# Q12# Q17 Q16 Q15 Q14 Q13 Q12
Cypress Semiconductor Corporation Document #: 38-07514 Rev. *A
·
3901 North First Street
·
San Jose, CA 95134
· 408-943-2600 Revised April 16, 2003
PRELIMINARY
Pin Description
Pin 4,5 7,8 3 Name CLKA, CLKA# I/O I,PD[1] I,PC CLKB, CLKB# I,PD I,PC CLK_SEL I,PD O,OS HSTL ECL/PECL ECL/PECL Type ECL/PECL
FastEdgeTM Series CY2DP3120
Description Default differential clock input pair Alternate differential clock input pair CLK Mux select True output
52,50,48,46,44,42,39,3 Q[0-19] 7,35,33,31,29,26,24,22 ,20,18,16,13,11 51,49,47,45,43,41,38,3 Q#[0-19] 6,34,32,30,28,25,23,21 ,19,17,15,12,10 6 9 2 1,14,27,40 VBB[3] VEE[2] VCC VCCO
O,OS
ECL/PECL
Complement output
O -PWR +PWR +PWR
Bias Power Power Power
Reference voltage output for single-ended ECL or PECL operation Power supply, negative connection Power supply, positive connection Power supply, positive connection
Governing Agencies
The following agencies provide specifications that apply to the CY2DP3120. The agency name and relevant specification is listed below. Agency Name JEDEC Specification JESD 51 (Theta JA) JESD 82 (ECL) JESD 65A (Skew,Jitter)
JESD 8-6 (HSTL)
IEEE UL MilSpec 1596.3 (Jitter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Thermal Theta JC)
Notes: 1. In the I/O column, the following notation is used: I = Input, O = Output, PD = Pull-down, PU = Pull-up, PC = Pull Center, O = Output, OS = Open Source, PWR = Power. 2. in ECL mode (negative power supply mode), VEE is either 3.3V or 2.5V and VCC is connected to GND(0V). In PECL mode (positive power supply mode), VEE is connected to GND(0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single ended bias mode when VCC is +3.3V.
Document #: 38-07514 Rev. *A
Page 2 of 11
PRELIMINARY
Absolute Maximum Conditions
Parameter Vcc Vcc VBB IBB VTT VIN VOUT LUI TS TA TJ ØJc ØJa ESDh MSL GATES UL94 FIT Description Supply Voltage Operating Voltage Output Reference Voltage Output Reference Current Output Termination Voltage Input Voltage Output Voltage Latch-up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Flammability Rating Failure in Time Assembled Die @1/8 in Manufacturing Test Condition Non-functional Functional Relative to VCC Relative to VBB VTT = 0V for VCC = 2.5V Relative to VCC Relative to VCC Functional Non-functional Functional Functional Functional Functional
FastEdgeTM Series CY2DP3120
Min. 0.3 2.5 5% VCC1.525 Max. 3.6 3.3 + 5% Vcc1.325 200 VCC2 0.3 0.3 300 65 40 10 TBD TBD 2000 TBD 50 V0 TBD +150 +85 +110 VCC+0.3 VCC+0.3 Unit VDC VDC VDC uA VDC VDC VDC mA °C °C °C °C/W °C/W V N.A. Ea. N.A. PPM
PECL DC Electrical Specifications
Parameter VIL VIH II N VPP VCMR II N VOH VOL Description Input Voltage, Low Input Voltage, High Input Current[4] Differential Input Voltage[5] Differential Cross Point Voltage[6] Input Current
[4]
Condition
Min. VCC1.945
Max. VCC1.625 VCC0.880 200
Unit V V uA
Define VCC and Load Current VCC1.165 VIN = VIL or VIN = VIH Differential Operation Differential Operation VIN = VIL or VIN = VIH IOH = 30 mA[9], 50 Load IOL = 5 ma[9],50 Load VCC1.145 VCC1.945 VCC 1.945 0.4
[8]
Clock input pair CLKA, CLKA#,CLKB, CLKB# (PECL Differential Signals) 0 .1 1 .2 1 .3 VCC 200 V V uA
PECL Outputs Q0-Q19, (Q0-Q19)#(PECL Differential Signals) Output High Voltage Output Low Voltage VCC = 3.3V ±5%VCC = 2.5V ±5% Differential Input Voltage[7] Differential Cross Point Voltage Input Current Vin = Vx ± 0.2V VCC0.895 VCC1.695 VCC1.695 1 .9 0.9 200 V V
Clock Input Pair CLKA, CLKA#,CLKB, CLKB# (HSTL Differential Signals) VDIF VX II N V V uA 0.68
Notes: 4. Input have internal pullup / pulldown or biasing resistors which affect the input current. 5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 7. VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality. 8. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 9. Equivalent to a termination of 50 to VTT.
Document #: 38-07514 Rev. *A
Page 3 of 11
PRELIMINARY
PECL DC Electrical Specifications (continued)
Parameter Supply Current and VBB IEE VBB Ipup Ipdwn CIN COUT LIN ZOUT Maximum Quiescent Supply Current without Output Termination Current[10] Output Reference Voltage Internal Pull-up Current Internal Pull-down Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Output Impedance Q0Q19, (Q0Q19)# Q0Q19, (Q0Q19)# VEE Pin IBB = 200 uA Description Condition
FastEdgeTM Series CY2DP3120
Min. Max. Unit
130 VCC1.525 TBD TBD TBD TBD TBD TBD VCC1.325 TBD TBD TBD TBD TBD TB D
mA V mA. mA. pF pF nH
ECL DC Electrical Specifications
Parameter VIL VIH II N VPP VCMR II N VOH VOL Description Input Voltage, Low Input Voltage, High Input Current[11] VIN = VIL or VIN = VIH Differential Operation Differential Operation VIN = VIL or VIN = VIH IOH = 30 mA[14] IOL = 5 ma
[14]
Condition
Min. 1.945 1.165
Max. 1.625 0.880 200
Unit V V uA
Clock input pair CLKA, CLKA#,CLKB, CLKB# (ECL Differential Signals) Differential Input Voltage[12] Differential Cross Point Voltage[13] Input Current
[11]
0 .1 VEE+1.2
1 .3 0 200
V V uA
ECL Outputs Q0-Q19, (Q0-Q19)# (ECL Dfferential Signals) Output High Voltage Output Low Voltage VEE = 3.3V ±5% VEE = 2.5V ±5% Maximum Quiescent Supply Current without Output Termination Current[15] Output Reference Voltage 1.145 1.945 1.945 0.895 1.695 1.695 V V
Supply Current and VBB IEE VBB VEE Pin IBB = 200 uA 1.525 130 1.325 mA V
Notes: 10. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH VTT)/Rload + (VOL VTT)/Rload +IEE. 11. Input have internal pull-up/pull-down or biasing resistors which affect the input current. 12. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 13. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 14. Equivalent to a termination of 50 to VTT. 15. ICC Calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH VTT)/Rload + (VOL VTT)/Rload +IEE.
Document #: 38-07514 Rev. *A
Page 4 of 11
PRELIMINARY
AC Electrical Specifications
Parameter VPP VCMR FCLK TPD Description Differential Input Voltage[17] Differential Cross Point Voltage Input Frequency[19] Propagation Delay CLKA or CLKB to Q0Q9 Pair
[18]
FastEdgeTM Series CY2DP3120
Condition Differential Operation Differential Operation 50% Duty Cycle Standard Load 660 MHz 50% Duty Cycle Standard Load Differential Operation Differential Operation Differential Operation 50% Duty Cycle Standard Load 660 MHz 50% Duty Cycle Standard Load Differential Operation Differential PRBS fo < 50 MHz fo < 0.8 GHz fo < 1.0 GHz 660-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Standard Load Differential Operation 660-MHz 50% Duty Cycle Differential 20% to 80% 660-MHz 50% Duty Cycle Standard Load
Min. 0 .1 VEE+1.2 400
Max. 1 .3 0 1,500 750
Unit V V MHz ps
Clock Input Pair CLKA, CLKA (PECL or ECL Differential Signals)
Clock Input Pair CLKB, CLKB (HSTL Differential Signals) VPP VCMR FCLK TPD Differential Input Voltage[17] Differential Cross Point Voltage[18] Input Frequency
[19]
0 .1 VEE+1.2 400
1 .3 0 1,500 750
V V MHz ps
Propagation Delay CLKA or CLKB to Q0Q9 Pair
ECL/PECL Clock Outputs (Q019, Q#019) (Differential) Vo(P-P) Differential Output Voltage (Peak-to-Peak) 0.45 0.4 0.375 50 V
tsk(O)
Output-to-Output skew
ps
tsk(PP)
Output-to-output skew (part-to-part)
500
ps
Tjitt(cc)
Output cycle-to-cycle jitter (Intrinsic)
10
ps r.m.s ps
tsk(P)
Output pulse skew[21]
TF, TF TTB
Output Rise/Fall time Total Timing Budget
0.3
ns ps
Notes: 16. AC characteristics apply for parallel output termination of 50 to VTT. 17. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew. 18. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew. 19. The CY2DP3120 is fully operation up to 1.5 GHz. 20. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. 21. Output pulse skew is the absolute difference of the propagation delay times: | tPLH tPHL |.
Document #: 38-07514 Rev. *A
Page 5 of 11
Others parts begin by cy
CY-1 CY-2 CY-3 CY-4 CY-5 CY-6 CY-7 CY-8 CY-9 CY-10 CY-11 CY-12 CY-13 CY-14 CY-15 CY-16 CY-17 CY-18 CY-19 CY-20 CY-21 CY-22 CY-23 CY-24 CY-25 CY-26 CY-27 CY-28 CY-29 CY-30 CY-31 CY-32 CY-33 CY-34 CY-35 CY-36 CY-37 CY-38 CY-39 CY-40 CY-41 CY-42 CY-43 CY-44 CY-45 CY-46 CY-47 CY-48 CY-49 CY-50 CY-51 CY-52
|
|
|
