Details, datasheet, quote on part number: CY38050V484-125BBI
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD)
DescriptionQuantum38K CPLD
CompanyCypress Semiconductor Corp.
DatasheetDownload CY38050V484-125BBI datasheet
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Features, Applications


High density to 100K usable gates to 1536 macrocells to 302 maximum I/O pins Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan Embedded memory to 48-Kb embedded dual-port channel memory 125-MHz in-system operation AnyVoltTM interface 3.3V and 2.5V VCC operation 3.3V, 2.5V and 1.8V I/O capability Low-power operation 0.18-mm 6-layer metal SRAM-based logic process Full-CMOS implementation of product term array Simple timing model No penalty for using full 16 product terms/macrocell No delay for single product term steering or sharing Flexible clocking Four synchronous clocks per device Locally generated product term clock Clock polarity control at each register Carry-chain logic for fast and efficient arithmetic operations Multiple I/O standards supported LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI Compatible with NoBLTM, ZBTTM, and QDRTM SRAMs Programmable slew rate control on each I/O pin User-programmable Bus Hold capability on each I/O pin Fully 3.3V PCI-compliant (as per PCI spec rev. 2.2) Compact PCI hot swap ready Multiple package/pinout offering across all densities to 484 pins in PQFP and FBGA packages Simplifies design migration across density In-System ReprogrammableTM (ISRTM) JTAG-compliant on-board configuration Design changes do not cause pinout changes IEEE1149.1 JTAG boundary scan Pin-to-pin-compatible with Cypress's high-end Delta39KTM CPLDs allowing easy migration path to More embedded memory Spread AwareTM PLL Higher density and higher speed devices High speed I/O standards and more

Warp® IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing Active-HDL FSM graphical finite state machine editor Active-HDL SIM post-synthesis timing simulator Architecture Explorer for detailed design analysis Static Timing Analyzer for critical path analysis Available on Windows 98TM, Windows NTTM, Windows METM, Windows 2000TM, and Sun Solaris 2.5 and later for $99 Supports all Cypress programmable logic products

Typical 23K­72K 46K­144K Channel memory (Kb) 24 48 Maximum I/O Pins 302 fMAX2 (MHz) 125 Speed tPD Pin-to-Pin (ns) 10 Standby 10 mA

Notes: 1. Upper limit of typical gates is calculated by assuming that only 50% of the channel memory is used. 2. Standby ICC values are with no output load and stable inputs.

Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs

Note: 3. Speed bins shown here are for commercial operating ranges. Please refer to the Quantum38K Part Numbers (Ordering Information) on page 24 for industrial-range speed bins.

Figure 1. Quantum38K100 Block Diagram (3 Rows x 4 Columns) with I/O Bank Structure


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