Details, datasheet, quote on part number: CY39100Z484B-125BBI
DescriptionCPLDS at Fpga Densities Delta39K Isr CPLD Family
CompanyCypress Semiconductor Corp.
DatasheetDownload CY39100Z484B-125BBI datasheet


Features, Applications


High density to 200K usable gates to 3072 macrocells to 428 maximum I/O pins Twelve dedicated inputs including four clock pins, four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfigurability Embedded memory to 480K bits embedded SRAM to 384K bits of (single-port) cluster memory to 96K bits of (dual-port) channel memory High speed ­ 233-MHz in-system operation AnyVoltTM interface 3.3V, 2.5V, and 1.8V VCC versions available & 1.5V I/O capability on all versions Low-power operation 0.18-µm six-layer metal SRAM-based logic process Full-CMOS implementation of product term array Standby current as low at 1.8V VCC Simple timing model No penalty for using full 16 product terms / macrocell No delay for single product term steering or sharing Flexible clocking Spread AwareTM PLL drives all four clock networks Allows 0.6% spread spectrum input clocks Several multiply, divide and phase shift options Offered with 3.3/2.5V versions only Four synchronous clock networks per device Locally generated product term clock Clock polarity control at each register Carry-chain logic for fast and efficient arithmetic operations Multiple I/O standards supported LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ Compatible with NOBLTM, ZBTTM, and QDRTM SRAMs Programmable slew rate control on each I/O pin User-Programmable Bus Hold capability on each I/O pin Fully PCI compliant (to 66 MHz 64-bit PCI spec, rev. 2.2) CompactPCI hot swap ready Multiple package/pinout offering across all densities to 676 pins in PQFP, BGA, and FBGA packages Same pinout for 3.3V/2.5V and 1.8V devices Simplifies design migration across density Self-BootTM solution in BGA and FBGA packages In-System ReprogrammableTM (ISRTM) JTAG-compliant on-board programming Design changes don't cause pinout changes IEEE1149.1 JTAG boundary scan

Warp® IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing Active-HDL FSM graphical finite state machine editor Active-HDL SIM post-synthesis timing simulator Architecture Explorer for detailed design analysis Static Timing Analyzer for critical path analysis Available on Windows 95/98/2000/XPTM and Windows NTTM for $99 Supports all Cypress programmable logic products

Typical ­ 288K Cluster memory (Kbits) Channel memory (Kbits) Maximum I/O Pins fMAX2 (MHz) Speed - tPD Pin-to-Pin (ns) Standby 4 mA

Notes: 1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. Standby ICC values are with PLL not utilized, no output load and stable inputs.

Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs

Notes: 3. Speed bins shown here are for commercial operating range. Please refer to Delta39KTM Ordering information on industrial-range speed bins on page 40. 4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000 programming/erase cycles and can retain data for at least 100 years.

Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure

The Delta39KTM family, based a 0.18-µm, six-layer metal CMOS logic process, offers a wide range of high-density solutions at unparalleled system performance. The Delta39K family is designed to combine the high speed, predictable timing, and ease of use of CPLDs with the high densities and low power of FPGAs. With devices ranging from to 200,000 usable gates, the family features devices ten times the size of previously available CPLDs. Even at these large Document 38-03039 Rev. *D

densities, the Delta39K family is fast enough to implement a fully synthesizable 64-bit, 66-MHz PCI core. The architecture is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H and V) routing channels. Each LBC features eight individual Logic Blocks (LB) and two cluster memory blocks. Adjacent to each LBC is a channel memory block, which can be accessed directly from the I/O pins. Both types of memory blocks are highly configurable and can be cascaded in width and depth. See Figure 1 for a block diagram of the Delta39K architecture. Page of 91


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