|Description||512K / 1 Mbit CPLD Boot EePROM|
|Company||Cypress Semiconductor Corp.|
|Datasheet||Download CY3LV010 datasheet
EE Reprogrammable x 1- and x 1-bit Serial Memories Designed to Store Configuration Data for Complex Programmable Logic Devices (CPLDs) In-System Programmable via two-wire Bus using Cypress's CYDH2200E Programming Kits Simple Interface to SRAM-based CPLDs Compatible with Cypress & Quantum38KTM CPLDs Cascadable Read-Back to Support Higher-density CPLDs Low-power CMOS EEPROM Process Available in PLCC Package (Pin Compatible Across Product Family) Operate at 3.3V VCC System-friendly READY Pin Low-power Standby Mode
The CY3LV512/010 (high-density CY3LV Series) CPLD boot EEPROMs provide an easy-to-use, cost-effective configuration memory for Complex Programmable Logic Devices. The CY3LV Series is packaged in the popular 20-pin PLCC. These devices support a system-friendly READY pin, which signifies a "good" power level to the CPLD and can be used to ensure reliable system power-up. The CY3LV Series boot PROMs can be programmed with industry-standard programmers or Cypress's CYDH2200E CPLD boot PROM programming kit. Please refer to the data sheet "CYDH2200E CPLD Boot PROM Programming Kit" for details.Controlling the CY3LV CPLD Boot PROMs During Configuration
Most connections between the CPLD device and the CY3LV boot PROM are simple and self-explanatory. Figure 1 shows the five signal interface required between the Delta39K/Quantum38K CPLD and the CY3LV boot PROM device. The DATA output of the boot PROM drives DATA input of the CPLD The master CPLD CCLK output drives the CLK input of the boot PROM The CPLD CCE pin drives the CE input of the boot PROM The RESET/OE input of the boot PROM is driven by the CPLD RESET pin The READY pin of the boot PROM is connected to the RECONFIG pin of the CPLD The READY pin is available as an open-collector indicator of the device's RESET status; it is driven LOW while the device is in its POWER-ON RESET cycle and released (three-stated) when the cycle is complete. The rising edge of the READY (hence RECONFIG) signal causes the CPLD to start configuring. The CONFIG_DONE, CCE and RESET output of the CPLD are set LOW, CCLK is activated and CPLD starts receiving configuration data on the DATA pin. After all the configuration data is shifted in, the CPLD device deactivates the CCLK and sets CCE, RESET and CONFIG_DONE HIGH. A HIGH level on the RESET/OE input during CPLD reset clears the boot PROM's internal address pointer and subsequent reconfiguration starts at the beginning. The CEO output of any CY3LV drives the CE input of the next in a cascade chain of EEPROMs. SER_EN must be connected to VCC, (except during In-System Programming).
The I/O and logic functions of the CPLD and their associated interconnections are established by loading configuration data (bitstream) into the CPLD. This configuration data is loaded either automatically upon power-up, or upon issuing JTAGcommand. The configuration data is stored in the internal Flash memory (Self-Boot packages only) or in the external CPLD boot PROM memory. This data is loaded from the appropriate memory depending on the state of the CPLD mode select pin (MSEL). In Master Serial mode (when MSEL=1), the CPLD automatically loads the configuration program from an external memory i.e., CY3LV CPLD boot PROM. These PROMs have been designed for compatibility with the Master Serial Mode. This document discusses the interface between Cypress's SRAM based CPLDs (Quantum38K and Delta39K) and CY3LV PROMs. For more details on the other modes of configuration of these CPLDs please refer to the application note titled "Configuring Delta39K/Quantum38K."DATA Reset DELTA39K/ CCE QUANTUM38K CCLK TCLK TMS TDI TDO MSEL Reconfig Config_Done GND 1µ F
Figure 1. Interface between Delta39K/Quantum38K CPLD and CY3LV boot PROM
Note: Currently, 3 revisions of Delta39K100 and 2 revisions of Quantum38K100 devices are available marked CY39100Vxxx, CY39100VxxxA, and CY39100VxxxB, CY38100Vxxx, and CY38100VxxxB. Figure 1 set-up represents the interface between CY39100VxxxB/CY38100VxxxB and CY3LV device. To get details on interface between other versions and CY3LV please refer to the application note titled "Configuring Delta39K/Quantum38K." Setup in Figure 1 also represents the interface between all other devices in Delta39K/Quantum38K families and CY3LV boot PROMs.
The CY3LV Series CPLD boot PROMs allow the user to program the reset polarity as either RESET/OE or RESET/OE.Cypress's SRAM based CPLDs (Delta39K and Quantum38K) require the RESET pin to be programmed active-High, i.e. as RESET/OE. CY3LV boot PROMs are shipped from the factory with the reset polarity programmed active-High. This polarity can be verified using industry standard programmers or Cypress's CYDH2200E boot PROM programming kit. Note: Every time the boot PROM is reprogrammed, care should be taken to select the reset polarity to be "HIGH" programmer software.
For future CPLDs requiring larger configuration memories, cascaded CPLD boot PROMs provide additional memory. As the last bit from the first boot PROM is read, the clock signal to the boot PROM asserts its CEO output LOW and disables its DATA line driver. The second boot PROM recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded boot PROMs are reset if the RESET/OE on each boot PROM is driven to its active (HIGH) level.
The programming mode is entered by bringing SER_EN LOW. In this mode the chip can be programmed by the two-wire serial bus. The programming is done at VCC (3.3V nominal) supply only. The CY3LV parts are read/write at 3.3V nominal.
The CY3LV enters a low-power standby mode whenever CE is asserted High. In this mode, the boot PROM consumes less than mA of current at 3.3V with CMOS level inputs. The output remains in a high-impedance state regardless of the state of the OE input.
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