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Part: CY7B923-155JI
Category:
Communication
-> Fiber Optics
-> Fiber Channel
Description: Hotlink Transmitter/receiver
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7B923-155JI datasheet File size : 207 kB
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CY7B923 CY7B933
HOTLink Transmitter/Receiver
Features
· · · · · · · · · · · · · · · · · · Fibre-Channel-compliant IBM ESCON-compliant DVB-ASI-compliant ATM-compliant 8B/10B-coded or 10-bit unencoded Standard HOTLink: 160330 Mbps High-speed HOTLink: 160400 Mbps for high-speed applications Low-speed HOTLink: 150160 Mbps for low-cost Fiber applications TTL synchronous I/O No external phase locked-loop (PLL) components Triple PECL 100K serial outputs Dual PECL 100K serial inputs Low power: 350 mW (Tx), 650 mW (Rx) Compatible with fiber-optic modules, coaxial cable, and twisted pair media Built-In Self-Test Single +5V supply 28-pin SOIC/PLCC/LCC 0.8µ BiCMOS twisted pair). Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also available for high-speed applications (160-400 Mbits/second), as well as for those low-Cost applications HOTLink-155 (150-160 Mbits/second operations). Figure 1 illustrates typical connections to host systems or controllers. Eight bits of user data or protocol information are loaded into the HOTLink transmitter and are encoded. Serial data is shifted out of the three differential positive ECL (PECL) serial ports at the bit rate (which is ten times the byte rate). The HOTLink receiver accepts the serial bit stream at its differential line receiver inputs and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized, decoded, and checked for transmission errors. Recovered bytes are presented in parallel to the receiving host along with a byte-rate clock. The 8B/10B encoder/decoder can be disabled in systems that already encode or scramble the transmitted data. I/O signals are available to create a seamless interface with both asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator and checker allows testing of the transmitter, receiver, and the connecting link as a part of a system diagnostic check. HOTLink devices are ideal for a variety of applications where a parallel interface can be replaced with a high-speed point-to-point serial link. Applications include interconnecting workstations, servers, mass storage, and video transmission equipment.
Functional Description
The CY7B923 HOTLink Transmitter and CY7B933 HOTLink Receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and
CY7B923 Transmitter
D0- 7 (Db - h) RP ENN ENA SC/D (Da) SVS (Dj) FOTO
CY7B933 Receiver Logic Block Diagram
RF A/B INA+ INA- INB (INB+) SI(INB- ) PECL TTL
DATA
FRAMER
CKW
ENABLE INPUT REGISTER
SHIFTER DECODER REGISTER
ENCODER CLOCK GENERATOR SHIFTER SO OUTA OUTB OUTC MODE BISTEN TEST LOGIC B9231 REFCLK MODE BISTEN
CLOCK SYNC
DECODER
TEST LOGIC
OUTPUT REGISTER
CKR
RDY
Q0- 7 (Qb - h)
RVS(Qj) SC/D (Qa) B9232
Cypress Semiconductor Corporation Document #: 38-02017 Rev. *B
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600 March 27,2002
CY7B923 CY7B933
PROTOCOL LOGIC
7B923 TRANSMIT ER T
TRANSMIT MESSAGE BUFFER
7B933 RECEIVER
HOST
B9233
SERIAL LINK HOST
Figure 1. HOTLink System Connections
CY7B923 Transmitter Pin Configurations
SOIC Top View
OUTB- O U T C- OUTC+ VCCN BISTEN GND MO DE RP VCCQ SVS(D j) (Dh) D7 (Dg)D 6 (Df)D 5 (Di)D 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 7B923 28 27 26 25 24 23 22 21 20 19 18 17 16 15
CY7B933 Receiver Pin Configurations
SOIC Top View
OUTB+ OUTA+ OUTA- FOTO E NN E NA VCCQ CK W GND SC/D(D a) D0 (Db) D1 (Dc) D2 (Dd) D3 (De)
B9235
INA- INA+ A/B BISTEN RF GND RDY GND VCCN R V S ( Q j) (Qh) Q7 (Qg) Q6 (Qf) Q5 (Qi) Q4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 7B933
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PLCC/LCC Top View
VCCN OUTC+ O U T C- OUTB- OUTB+ OUTA+ OUTA-
PLCC/LCC Top View
BISTEN A/B INA+ INA- INB (INB+) SI (INB-) MO DE
4 3 2 1 28 2726
BISTEN GND MODE RP VCCQ SVS(D j) (Dh)D 7
5 6 7 7B923 8 9 10 11 1213 14 15 16 1718
25 24 23 22 21 20 19
FOTO E NN E NA VCCQ CK W GND SC/D(D a)
B9234
4 3 2 1 28 2726
(Dg ) D 6 (D f ) D 5 (D i ) D 4 (D e ) D 3 (Dd ) D 2 (D c ) D 1 (Db ) D 0
RF GND RDY GND VCCN R V S ( Q j) (Qh) Q7
5 6 7 7B933 8 9 10 11 1213 14 15 16 1718
25 24 23 22 21 20 19
Document #: 38-02017 Rev. *B
(Q g ) Q 6 (Q f ) Q 5 (Q i ) Q 4 (Q e ) Q 3 (Q d ) Q 2 (Q c ) Q 1 (Q b ) Q 0
RECEIVE MESSAGE BUFFER
INB(INB+) SI(INB- ) MODE REFCLK VCCQ SO CK R VCCQ GND SC/D (Qa) Q 0 (Q b ) Q 1 (Q c ) Q 2 (Q d ) Q3 (Qe)
B9237
REFCLK VCCQ SO CK R VCCQ GND SC/D (Qa)
B9236
Page 2 of 36
PROTOCOL LOGIC
CY7B923 CY7B933
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..... - 65°C to +150°C Ambient Temperature with Power Applied........-55°C to +125°C Supply Voltage to Ground Potential ....... - 0.5V to +7.0V DC Input Voltage ...... - 0.5V to +7.0V Output Current into TTL Outputs (LOW)....30 mA Output Current into PECL outputs (HIGH) ..........-50 mA Static Discharge Voltage ......... > 4001V (per MIL-STD-883, Method 3015) Latch-Up Current .... > 200 mA
Operating Range
Range Commercial Industrial Military Ambient Temperature 0°C to +70°C - 40°C to +85°C -55°C to +125°C Case Temperature VCC 5V ± 10% 5V ± 10% 5V ± 10%
Pin Descriptions
CY7B923 HOTLink Transmitter Name D0-7 (Db - h) SC/D (Da) I/O TTL In Description Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is sent. When MODE is HIGH, D0, 1, ...7 become Db, c,...h, respectively. Special Character/Data Select. A HIGH on SC/D when CKW rises causes the transmitter to encode the pattern on D0-7 as a control code (Special Character), while a LOW causes the data to be coded using the 8B/10B data alphabet. When MODE is HIGH, SC/D (Da) acts as Da input. SC/D has the same timing as D0-7. Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent while the data on the parallel inputs is ignored. If SVS is LOW, the state of D0-7 and SC/D determines the code sent. In normal or test mode, this pin overrides the BIST generator and forces the transmission of a Violation code. When MODE is HIGH (placing the transmitter in unencoded mode), SVS (Dj) acts as the Dj input. SVS has the same timing as D0-7. Enable Parallel Data. If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and sent. If ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null character (K28.5) to fill the space between user data. ENA may be held HIGH/LOW continuously or it may be pulsed with each data byte to be sent. If ENA is being used for data control, ENN will normally be strapped HIGH, but can be used for BIST function control. Enable Next Parallel Data. If ENN is LOW, the data appearing on D0-7 at the next rising edge of CKW is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D0-7 at the next rising edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space between user data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. If ENN is being used for data control, ENA will normally be strapped HIGH, but can be used for BIST function control. Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the high-speed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW must be connected to a crystal controlled time base that runs within the specified frequency range of the Transmitter and Receiver. Fiber Optic Transmitter Off. FOTO determines the function of two of the three PECL transmitter output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs continuously. If FOTO is HIGH, OUTA± and OUTB± are forced to their "logic zero" state (OUT+ = LOW and OUT- = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is unaffected by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
TTL In
SVS (Dj)
TTL In
ENA
TTL In
ENN
TTL In
CKW
TTL In
FOTO
TTL In
Document #: 38-02017 Rev. *B
Page 3 of 36
CY7B923 CY7B933
CY7B923 HOTLink Transmitter (continued) Name OUTA± OUTB± OUTC± I/O PECL Out Description Differential Serial Data Outputs. These PECL 100K outputs (+5V referenced) are capable of driving terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs can be left open, or wired to VCC to reduce power, if the output is not required. OUTA± and OUTB± are controlled by the level on FOTO, and will remain at their "logical zero" states when FOTO is asserted. OUTC± is unaffected by the level on FOTO. (OUTA+ and OUTB+ are used as a differential test clock input while in Test mode, i.e., MODE = UNCONNECTED or forced to VCC/2.) Encoder Mode Select. The level on MODE determines the encoding method to be used. When wired to GND, MODE selects 8B/10B encoding. When wired to VCC, data inputs bypass the encoder and the bit pattern on Da-j goes directly to the shifter. When left floating (internal resistors hold the input at VCC/2) the internal bit-clock generator is disabled and OUTA+/OUTB+ become the differential bit clock to be used for factory test. In typical applications MODE is wired to VCC or GND. Built-In Self-Test Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an alternating 1-0 pattern (D10.2 or D21.5). When either ENA or ENN is set LOW and BISTEN is LOW, the transmitter begins a repeating test sequence that allows the Transmitter and Receiver to work together to test the function of the entire link. In normal use this input is held HIGH or wired to VCC. The BIST generator is a free-running pattern generator that need not be initialized, but if required, the BIST sequence can be initialized by momentarily asserting SVS while BISTEN is LOW. BISTEN has the same timing as D0-7. Read Pulse. RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop. Power for output drivers. Power for internal circuitry. Ground.
MODE
ThreeLevel In
BISTEN
TTL In
RP
TTL Out
VCCN VCCQ GND
CY7B933 HOTLink Receiver Name Q0-7 (Qb - h) SC/D (Qa) I/O TTL Out TTL Out Description Q0-7 Parallel Data Output. Q0-7 contain the most recently received data. These outputs change synchronously with CKR. When MODE is HIGH, Q0, 1, ...7 become Qb, c,...h respectively. Special Character/Data Select. SC/D indicates the context of received data. HIGH indicates a Control (Special Character) code, LOW indicates a Data character. When MODE is HIGH (placing the receiver in Unencoded mode), SC/D acts as the Qa output. SC/D has the same timing as Q0-7. Received Violation Symbol. A HIGH on RVS indicates that a code rule violation has been detected in the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW on RVS indicates correct operation of the Transmitter, Receiver, and link on a byte-by-byte basis. When MODE is HIGH (placing the receiver in Unencoded mode), RVS acts as the Qj output. RVS has the same timing as Q0-7. Data Output Ready. A LOW pulse on RDY indicates that new data has been received and is ready to be delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted by the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last byte of a test loop and will pulse HIGH one byte time per BIST loop. Clock Read. This byte rate clock output is phase and frequency aligned to the incoming serial data stream. RDY, Q0-7, SC/D, and RVS all switch synchronously with the rising edge of this output. Serial Data Input Select. This PECL 100K (+5V referenced) input selects INA or INB as the active data input. If A/B is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If A/B is LOW INB is selected. Serial Data Input A. The differential signal at the receiver end of the communication link may be connected to the differential input pairs INA± or INB±. Either the INA pair or the INB pair can be used as the main data input and the other can be used as a loopback channel or as an alternative data input selected by the state of A/B. One input of an intentionally unused differential-pair (INA± or INB±) should be terminated to VCC through a 1-5 K resistor to assure that no data transitions are accidentally created. Page 4 of 36
RVS (Qj)
TTL Out
RDY
TTL Out
CKR A/B
TTL Out PECL in
INA±
Diff In
Document #: 38-02017 Rev. *B
CY7B923 CY7B933
CY7B933 HOTLink Receiver (continued) Name INB (INB+) I/O PECL in (Diff In) Description Serial Data Input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB differential pair. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5V referenced) serial data input. INB is used as the test clock while in Test mode. Status Input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB differential pair. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably with INA±. If SO is normally connected and loaded, SI becomes a single-ended PECL 100K (+5V referenced) status monitor input, which is translated into a TTL-level signal at the SO pin. Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded (without any external pull-up resistor), SO will assume the same logical level as SI and INB will become a single-ended PECL serial data input. If the status monitor translation is not desired, then SO may be wired to VCC and the INB± pair may be used as a differential serial data input. Reframe Enable. RF controls the Framer logic in the Receiver. When RF is held HIGH, each SYNC (K28.5) symbol detected in the shifter will frame the data that follows. If it is HIGH for 2,048 consecutive bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic is disabled. The incoming data stream is then continuously deserialized and decoded using byte boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC characters to reframe the data erroneously. Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL. REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream. REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within CKW ± 0.1%). Decoder Mode Select. The level on the MODE pin determines the decoding method to be used. When wired to GND, MODE selects 8B/10B decoding. When wired to VCC, registered shifter contents bypass the decoder and are sent to Qa-j directly. When left floating (internal resistors hold the MODE pin at VCC/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory test. In typical applications, MODE is wired to VCC or GND. Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST loop) character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver, and the link connecting them. In BIST mode the status of the test can be monitored with RDY and RVS outputs. In normal use BISTEN is held HIGH or wired to VCC. BISTEN has the same timing as Q0-7. Power for output drivers. Power for internal circuitry. Ground. In BIST mode, the Input register becomes the signature pattern generator by logically converting the parallel Input register into a Linear Feedback Shift Register (LFSR). When enabled, this LFSR will generate a 511-byte sequence that includes all Data and Special Character codes, including the explicit violation symbols. This pattern provides a predictable but pseudo-random sequence that can be matched to an identical LFSR in the Receiver. Encoder The Encoder transforms the input data held by the Input register into a form more suitable for transmission on a serial interface link. The code used is specified by ANSI X3.230 (Fibre Channel) and the IBM ESCON channel (code tables are at the end of this datasheet). The eight D0-7 data inputs are converted to either a Data symbol or a Special Character, depending upon the state of the SC/D input. If SC/D is HIGH, the data inputs represent a control code and are encoded using the Special Character code table. If SC/D is LOW, the data inputs are Page 5 of 36
SI (INB-)
PECL in (Diff In)
SO
TTL Out
RF
TTL In
REFCLK
TTL In
MODE
ThreeLevel In
BISTEN
TTL In
VCCN VCCQ GND
CY7B923 HOTLink Transmitter Block Diagram Description
Input Register The Input register holds the data to be processed by the HOTLink transmitter and allows the input timing to be made consistent with standard FIFOs. The Input register is clocked by CKW and loaded with information on the D0-7, SC/D, and SVS pins. Two enable inputs (ENA and ENN) allow the user to choose when data is loaded in the register. Asserting ENA (Enable, active LOW) causes the inputs to be loaded in the register on the rising edge of CKW. If ENN (Enable Next, active LOW) is asserted when CKW rises, the data present on the inputs on the next rising edge of CKW will be loaded into the Input register. If neither ENA nor ENN are asserted LOW on the rising edge of CKW, then a SYNC (K28.5) character is sent. These two inputs allow proper timing and function for compatibility with either asynchronous FIFOs or clocked FIFOs without external logic, as shown in Figure 5.
Document #: 38-02017 Rev. *B
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