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Part: CY7C09279-12AC
Category:
Memory
-> SRAM
-> 32 Kb
-> Multi-Port RAM
Description: 5V Synchronous Dual-port Memory
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C09279-12AC datasheet File size : 207 kB
Request For quote: Find where to buy CY7C09279-12AC
Datasheet text preview:
25/ 025 1
C Y 7C09279/89 C Y 7C09379/89
32K/64K x16/18 Synchronous Dual Port Static RAM
Features
· True dual-ported memory cells which allow simultaneous access of the same memory location · Six Flow-Through/Pipelined devices -- 32K x 16/18 organization (CY7C09279/379) -- 64K x 16/18 organization (CY7C09289/389) · Three Modes -- Flow-Through -- Pipelined -- Burst · Pipelined output mode on both ports allows fast 100MHz cycle time · 0.35-micron CMOS for optimum speed/power · High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.) · Low operating power -- Active = 195 mA (typical) -- Standby = 0.05 mA (typical) · Fully synchronous interface for easier operation · Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise · · · · · · -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and Lower Byte Controls for Bus Matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-compatible and functionally equivalent to IDT70927 and IDT709279
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
1
0/ 1
1
0/ 1
0
0
CE0R CE1R LBR OER
FT/PipeL
[2]
0/ 1
1b 0b 1a 0a
b a
0a 1a 0b 1b
a b
0/ 1
FT/PipeR
8/9
[2]
8/9
I/O8/9LI/O15/17L
[3]
I/O8/9RI/O15/17R
8/9 15/16
I/O Control
I/O Control
8/9 15/16
I/O0LI/O7/8L A0LA14/15L CLKL ADSL CNTENL CNTRSTL
[4]
I/O0RI/O7/8R Counter/ Address Register Decode Counter/ Address Register Decode A0RA14/15R CLKR ADSR CNTENR CNTRSTR
[4]
[3]
True Dual-Ported RAM Array
Notes: 1. See page 6 for Load Conditions. 2. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices. 3. I/O0I/O7 for x16 devices. I/O0I/O8 for x18 devices. 4. A0A14 for 32K; A0A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 Document #: 38-06040 Rev. ** Revised September 19, 2001
CY7C09279/89 CY7C09379/89
Functional Description
The CY7C09279/89 and CY7C09379/89 are high-speed synchronous CMOS 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[5] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/PIPE pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 A8L A7L A6L A5L A4L A3L A2L A1L A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [6] A15L NC NC LBL UBL CE0L CE1L CNTRSTL VCC R/WL OEL [7] FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9R A10R A11R A12R A13R A14R A15R [6] NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER FT/PIPER [7] GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
CY7C09289 (64K x 16) CY7C09279 (32K x 16)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/01R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O0R
I/O9R
GND
GND
VCC
VCC
I/O3L
I/O2L
I/O1L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
Notes: 5. When writing simultaneously to the same location, the final value cannot be guaranteed. 6. This pin is NC for CY7C09279. 7. For CY7C09279, pin #18 connected to VCC is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flowthrough device.
Document #: 38-06040 Rev. **
I/O4L
I/O0L
NC
Page 2 of 18
CY7C09279/89 CY7C09379/89
Pin Configurations (continued)
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L A14L [8] A15L LBL UBL CE0L CE1L CNTRSTL R/WL OE L VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 A8R A9R A10R A11R A12R A13R A14R A15R LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R [8]
CY7C09389 (64K x 18) CY7C09379 (32K x 18)
A7R 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/10R
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09279/89 CY7C09379/89 -6[1] fMAX2 (MHz) (Pipelined) Max Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level)
Note: 8. This pin is NC for CY7C09379.
CY7C09279/89 CY7C09379/89 -7 83 7 .5 235 40 0.05
CY7C09279/89 CY7C09379/89 -9 67 9 215 35 0.05
I/O9R
I/01R
VCC
GND
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC
CY7C09279/89 CY7C09379/89 -12 50 12 195 30 0.05
100 6.5 250 45 0.05
Document #: 38-06040 Rev. **
Page 3 of 18
CY7C09279/89 CY7C09379/89
Pin Definitions
Left Port A0LA15L ADSL Right Port A0RA15R ADSR Description Address Inputs (A0A14 for 32K, A0A15 for 64K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0I/O8 for x18, I/O0I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9LI/O15/17L). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)..... 20 mA Static Discharge Voltage .......... >1100V Latch-Up Current..... >200 mA
CE0L,CE1L CLKL CNTENL
CE0R,CE1R CLKR CNTENR
CNTRSTL I/O0LI/O17L LBL
CNTRSTR I/O0RI/O17R LBR
UBL OEL R/WL FT/PIPEL GND NC VCC
UBR OER R/WR FT/PIPER
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......... 65°C to +150°C Ambient Temperature with Power Applied .. 55°C to +125°C Supply Voltage to Ground Potential ...... 0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ......... 0.5V to +7.0V DC Input Voltage........... 0.5V to +7.0V
Note: 9. Industrial parts are available in CY7C09289 and Cy7C09389 only
Operating Range
Range Commercial Industrial[9] Ambient Temperature 0°C to +70°C 40°C to +85°C VCC 5V ± 10% 5V ± 10%
Document #: 38-06040 Rev. **
Page 4 of 18
CY7C09279/89 CY7C09379/89
Electrical Characteristics Over the Operating Range
CY7C09279/89 CY7C09379/89 -6[1] Parameter VOH VOL VIH VIL IOZ ICC Description Output HIGH Voltage (VCC = Min., IOH = 4.0 mA) Output LOW Voltage (VCC = Min., IOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Com'l. Ind.[9] 45 115 40 105 10 250 2.2 0.8 10 450 10 235 2.4 0.4 2.2 0.8 10 420 10 215 245 35 50 175 235 160 220 145 160 0.05 0.5 0.05 0.5 0.05 0.05 160 200 145 185 130 145 2.4 0.4 2 .2 0 .8 10 360 410 95 110 205 220 0.5 0.5 170 185 110 150 0.05 0.5 125 190 30 85 10 195 -7 2 .4 0 .4 2.2 0.8 10 300 -9 2 .4 0 .4 -12 V V V V µA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
ISB1
Standby Current (Both Com'l. Ports TTL Level)[10] Ind.[9] CEL & CER VIH, f = f MAX Standby Current (One Com'l. Port TTL Level)[10] Ind.[9] CEL | CER VIH, f = f MAX Standby Current (Both Com'l. Ports CMOS Level)[10] Ind.[9] CEL & CER VCC 0.2V, f = 0 Standby Current (One Com'l. Port CMOS Level)[10] Ind.[9] CEL | CER VIH, f = f MAX
ISB2
ISB3
ISB4
Capacitance
Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 Unit pF
COUT Output Capacitance 10 pF Note: 10. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
Document #: 38-06040 Rev. **
Page 5 of 18
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