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Part: CY7C09279V-9AC
Category:
Memory
-> SRAM
-> 32 Kb
-> Multi-Port RAM
Description: Dual-port Memory 3.3V Synchronous
Company: Cypress Semiconductor Corp.
Datasheet: Download CY7C09279V-9AC datasheet File size : 207 kB
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Datasheet text preview:
25/ 025 1
CY7C09269V/79V/89V CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
Features
· True Dual-Ported memory cells which allow simultaneous access of the same memory location · 6 Flow-Through/Pipelined devices -- 16K x 16/18 organization (CY7C09269V/369V) -- 32K x 16/18 organization (CY7C09279V/379V) -- 64K x 16/18 organization (CY7C09289V/389V) · 3 Modes -- Flow-Through -- Pipelined -- Burst · Pipelined output mode on both ports allows fast 100-MHz operation · 0.35-micron CMOS for optimum speed/power · High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns (max.) · 3.3V low operating power -- Active = 115 mA (typical) -- Standby = 10 µA (typical) · Fully synchronous interface for easier operation · Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise · · · · · -- Supported in Flow-Through and Pipelined modes Dual Chip Enables for easy depth expansion Upper and Lower Byte Controls for Bus Matching Automatic power-down Commercial and Industrial temperature ranges Available in 100-pin TQFP
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
1
0/ 1
1
0/ 1
0
0
CE0R CE1R LBR OER
FT/PipeL
[3]
0/ 1
1b 0b 1a 0a
b a
0a 1a 0b 1b
a b
0/ 1
FT/PipeR
8/9
[3]
8/9
I/O8/9LI/O15/17L
[4]
I/O8/9RI/O15/17R
8/9
I/O Control
I/O Control
8/9 14/15/16
I/O0LI/O7/8L A0LA13/14/15L CLKL ADSL CNTENL CNTRSTL
[5]
I/O0RI/O7/8R
14/15/16
[4]
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
A0RA13/14/15R CLKR ADSR CNTENR CNTRSTR
[5]
Notes: 1. Call for availability. 2. See page 6 for Load Conditions. 3. I/O8I/O15 for x16 devices; I/O9I/O17 for x18 devices. 4. I/O0I/O7 for x16 devices. I/O0I/O8 for x18 devices. 5. A0A13 for 16K; A0A14 for 32K; A0A15 for 64K devices.
For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation · 3901 North First Street · San Jose · CA 95134 · 408-943-2600 Document #: 38-06056 Rev. ** Revised September 21, 2001
CY7C09269V/79V/89V CY7C09369V/79V/89V
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[6] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND A0R A1R A2R A3R A4R A5R A6R A7R A8R 75 74 73 72 71 70 69 68 67 66 A8L A7L A6L A5L A4L A3L A2L A1L A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L
[7] [8]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R A10R A11R A12R A13R A14R A15R NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
[9] [7] [8]
A14L A15L NC NC LBL UBL CE0L CE1L
CNTRSTL VCC R/WL OEL
[9]
CY7C09289V (64K x 16) CY7C09279V (32K x 16) CY7C09269V (16K x 16)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
I/01R
GND
GND
VCC
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
VCC
I/O7R
I/O8R
Notes: 6. When writing simultaneously to the same location, the final value cannot be guaranteed. 7. This pin is NC for CY7C09269V. 8. This pin is NC for CY7C09269V and CY7C09279V. 9. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible to an IDT 5V x16 flow-through device.
Document #: 38-06056 Rev. **
I/O0R
I/O9R
I/O3L
I/O2L
I/O1L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O0L
NC
Page 2 of 19
CY7C09269V/79V/89V CY7C09369V/79V/89V
Pin Configurations (continued)
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R 75 74 73 72 71 70 69 68 67 66 A 8L A 7L A 6L A 5L A 4L A 3L A 2L A 1L A 0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L
[10] [11]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R A9R A10R A11R A12R A13R A14R A15R LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
[10] [11]
A14L A15L LBL UBL CE0L CE1L
CY7C09389V (64K x 18) CY7C09379V (32K x 18) CY7C09369V (16K x 18)
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CNTRSTL R/WL OE L VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/01R
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V -6[1, 2] -7[2] -9 -12 fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (µA) (Both Ports CMOS Level) 100 6.5 83 7.5 67 9 50 12
175 25
155 25
135 20
I/O9R
I/10R
VCC
GND
GND
VCC
115 20
10 µA
10 µA
10 µA
10 µA
Notes: 10. This pin is NC for CY7C09369V. 11. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. **
Page 3 of 19
CY7C09269V/79V/89V CY7C09369V/79V/89V
Pin Definitions
Left Port A0LA15L ADSL Right Port A0RA15R ADSR Description Address Inputs (A0A14 for 32K, A0A13 for 16K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0I/O8 for x18, I/O0I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9LI/O15/17L). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)..... 20 mA Static Discharge Voltage .......... >1100V Latch-Up Current...... >200mA
CE0L,CE1L CLKL CNTENL
CE0R,CE1R CLKR CNTENR
CNTRSTL I/O0LI/O17L LBL
CNTRSTR I/O0RI/O17R LBR
UBL OEL R/WL FT/PIPEL GND NC VCC
UBR OER R/WR FT/PIPER
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......... 65°C to +150°C Ambient Temperature with Power Applied............55°C to +125°C Supply Voltage to Ground Potential ...... 0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ... 0.5V to VCC+0.5V DC Input Voltage.....0.5V to VCC+0.5V
Operating Range
Range Commercial Industrial Ambient Temperature 0°C to +70°C 40°C to +85°C VCC 3.3V ± 300 mV 3.3V ± 300 mV
Document #: 38-06056 Rev. **
Page 4 of 19
CY7C09269V/79V/89V CY7C09369V/79V/89V
Electrical Characteristics Over the Operating Range
CY7C09269V/79V/89V CY7C09369V/79V/89V -6[1, 2] Max. Min. Min. Typ. Parameter VOH VOL VIH VIL IOZ ICC Description Output HIGH Voltage (VCC = Min. lOH = 4.0 mA) Output LOW Voltage (VCC = Min. lOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max, IOUT = 0 mA) Outputs Disabled Com'l. Indust. 25 95 10 2.0 0.8 10 175 320 10 -7[2] Max. Min. Typ. -9 Max. Min. Typ. -12 Max. 0 .4 2.0 0.8 10 135 185 20 35 95 105 10 10 85 95 10 230 300 75 85 155 165 250 250 115 125 75 10 250 85 20 70 10 115 0 .8 10 Unit pF pF Typ. Unit V V V V µA mA mA mA 140 mA mA µA µA 100 mA mA
2.4 0.4
2.4 0 .4 2.0 0 .8 10 155 275 275 390 25 85 115 175 85 120
2.4 0.4 2.0
2.4
180 mA
ISB1
Standby Current (Both Com'l. Ports TTL Level)[12] CEL & Indust. CER VIH, f = fMAX Standby Current (One Port Com'l. TTL Level)[12] CEL | CER Indust. VIH, f = fMAX Standby Current (Both Com'l. Ports CMOS Level)[12] CEL Indust. & CER VCC 0.2V, f = 0 Standby Current (One Port Com'l. CMOS Level)[12] CEL | CER Indust. VIH, f = fMAX
ISB2
105 165 165 210
ISB3
10
250
10 10
250 250 125
ISB4
105 135
95
125 170
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 10 10
Note: 12. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
Document #: 38-06056 Rev. **
Page 5 of 19
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